// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Intel and sold by Intel or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition"

// DATE "08/09/2018 00:24:50"

// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module DE0_NANO (
	CLOCK_50,
	GPIO_0_D,
	GPIO_1_D,
	KEY);
input 	CLOCK_50;
output 	[33:0] GPIO_0_D;
input 	[33:20] GPIO_1_D;
input 	[1:0] KEY;

// Design Ports Information
// GPIO_0_D[0]	=>  Location: PIN_D3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[1]	=>  Location: PIN_C3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[2]	=>  Location: PIN_A2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[3]	=>  Location: PIN_A3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[4]	=>  Location: PIN_B3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[5]	=>  Location: PIN_B4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[6]	=>  Location: PIN_A4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[7]	=>  Location: PIN_B5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[8]	=>  Location: PIN_A5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[9]	=>  Location: PIN_D5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[10]	=>  Location: PIN_B6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[11]	=>  Location: PIN_A6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[12]	=>  Location: PIN_B7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[13]	=>  Location: PIN_D6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[14]	=>  Location: PIN_A7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[15]	=>  Location: PIN_C6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[16]	=>  Location: PIN_C8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[17]	=>  Location: PIN_E6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[18]	=>  Location: PIN_E7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[19]	=>  Location: PIN_D8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[20]	=>  Location: PIN_E8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[21]	=>  Location: PIN_F8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[22]	=>  Location: PIN_F9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[23]	=>  Location: PIN_E9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[24]	=>  Location: PIN_C9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[25]	=>  Location: PIN_D9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[26]	=>  Location: PIN_E11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[27]	=>  Location: PIN_E10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[28]	=>  Location: PIN_C11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[29]	=>  Location: PIN_B11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[30]	=>  Location: PIN_A12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[31]	=>  Location: PIN_D11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[32]	=>  Location: PIN_D12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_0_D[33]	=>  Location: PIN_B12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO_1_D[28]	=>  Location: PIN_M10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[29]	=>  Location: PIN_L13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[31]	=>  Location: PIN_K15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// KEY[1]	=>  Location: PIN_E1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// CLOCK_50	=>  Location: PIN_R8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// KEY[0]	=>  Location: PIN_J15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[32]	=>  Location: PIN_J13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[30]	=>  Location: PIN_J16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[33]	=>  Location: PIN_J14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[27]	=>  Location: PIN_N14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[26]	=>  Location: PIN_L14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[25]	=>  Location: PIN_P14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[22]	=>  Location: PIN_R14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[21]	=>  Location: PIN_P16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[20]	=>  Location: PIN_P15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[24]	=>  Location: PIN_N15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO_1_D[23]	=>  Location: PIN_N16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("DE0_NANO_6_1200mv_85c_v_slow.sdo");
// synopsys translate_on

wire \GPIO_1_D[28]~input_o ;
wire \GPIO_1_D[29]~input_o ;
wire \GPIO_1_D[31]~input_o ;
wire \KEY[1]~input_o ;
wire \CLOCK_50~input_o ;
wire \PLL_inst|altpll_component|auto_generated|wire_pll1_fbout ;
wire \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ;
wire \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ;
wire \driver|line_count[0]~10_combout ;
wire \driver|line_count[1]~13 ;
wire \driver|line_count[2]~14_combout ;
wire \driver|pixel_count[0]~10_combout ;
wire \driver|pixel_count[0]~11 ;
wire \driver|pixel_count[1]~12_combout ;
wire \driver|pixel_count[1]~13 ;
wire \driver|pixel_count[2]~14_combout ;
wire \driver|pixel_count[2]~15 ;
wire \driver|pixel_count[3]~16_combout ;
wire \driver|pixel_count[3]~17 ;
wire \driver|pixel_count[4]~18_combout ;
wire \driver|pixel_count[4]~19 ;
wire \driver|pixel_count[5]~20_combout ;
wire \driver|pixel_count[5]~21 ;
wire \driver|pixel_count[6]~22_combout ;
wire \driver|pixel_count[6]~23 ;
wire \driver|pixel_count[7]~24_combout ;
wire \driver|pixel_count[7]~25 ;
wire \driver|pixel_count[8]~26_combout ;
wire \driver|pixel_count[8]~27 ;
wire \driver|pixel_count[9]~28_combout ;
wire \driver|Equal0~1_combout ;
wire \driver|Equal0~2_combout ;
wire \driver|Equal0~0_combout ;
wire \KEY[0]~input_o ;
wire \driver|line_count[9]~17_combout ;
wire \driver|line_count[2]~15 ;
wire \driver|line_count[3]~18_combout ;
wire \driver|line_count[3]~19 ;
wire \driver|line_count[4]~20_combout ;
wire \driver|line_count[4]~21 ;
wire \driver|line_count[5]~22_combout ;
wire \driver|line_count[5]~23 ;
wire \driver|line_count[6]~24_combout ;
wire \driver|line_count[6]~25 ;
wire \driver|line_count[7]~26_combout ;
wire \driver|line_count[7]~27 ;
wire \driver|line_count[8]~28_combout ;
wire \driver|line_count[8]~29 ;
wire \driver|line_count[9]~30_combout ;
wire \Mult1|mult_core|_~1_combout ;
wire \driver|Equal1~0_combout ;
wire \driver|Equal1~1_combout ;
wire \Mult1|mult_core|_~0_combout ;
wire \driver|line_count[9]~16_combout ;
wire \driver|line_count[0]~11 ;
wire \driver|line_count[1]~12_combout ;
wire \driver|V_SYNC_NEG~1_combout ;
wire \driver|V_SYNC_NEG~0_combout ;
wire \driver|V_SYNC_NEG~2_combout ;
wire \driver|H_SYNC_NEG~0_combout ;
wire \driver|H_SYNC_NEG~1_combout ;
wire \Mult1|mult_core|romout[1][9]~0_combout ;
wire \Mult1|mult_core|romout[1][8]~1_combout ;
wire \Mult1|mult_core|romout[1][7]~2_combout ;
wire \Mult1|mult_core|_~2_combout ;
wire \Mult1|mult_core|romout[0][10]~4_combout ;
wire \Mult1|mult_core|romout[1][6]~3_combout ;
wire \Mult1|mult_core|romout[1][5]~5_combout ;
wire \Mult1|mult_core|romout[0][9]~6_combout ;
wire \Mult1|mult_core|romout[0][8]~7_combout ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1 ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~3 ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5 ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~7 ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~9 ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ;
wire \Mult1|mult_core|romout[2][5]~8_combout ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ;
wire \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ;
wire \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ;
wire \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ;
wire \Mult1|mult_core|romout[0][7]~9_combout ;
wire \Mult1|mult_core|romout[0][6]~10_combout ;
wire \Mult1|mult_core|romout[0][5]~11_combout ;
wire \Add3~1 ;
wire \Add3~3 ;
wire \Add3~5 ;
wire \Add3~7 ;
wire \Add3~9 ;
wire \Add3~11 ;
wire \Add3~13 ;
wire \Add3~15 ;
wire \Add3~17 ;
wire \Add3~18_combout ;
wire \GPIO_1_D[32]~input_o ;
wire \GPIO_1_D[33]~input_o ;
wire \pixel_data_RGB332[0]~0_combout ;
wire \is_lsb~feeder_combout ;
wire \is_lsb~q ;
wire \X_ADDR[0]~15_combout ;
wire \last_href~feeder_combout ;
wire \last_href~q ;
wire \GPIO_1_D[30]~input_o ;
wire \X_ADDR[13]~43_combout ;
wire \X_ADDR[0]~16 ;
wire \X_ADDR[1]~17_combout ;
wire \X_ADDR[1]~18 ;
wire \X_ADDR[2]~19_combout ;
wire \X_ADDR[2]~20 ;
wire \X_ADDR[3]~21_combout ;
wire \X_ADDR[3]~22 ;
wire \X_ADDR[4]~23_combout ;
wire \X_ADDR[4]~24 ;
wire \X_ADDR[5]~25_combout ;
wire \X_ADDR[5]~26 ;
wire \X_ADDR[6]~27_combout ;
wire \X_ADDR[6]~28 ;
wire \X_ADDR[7]~29_combout ;
wire \X_ADDR[7]~30 ;
wire \X_ADDR[8]~31_combout ;
wire \X_ADDR[8]~32 ;
wire \X_ADDR[9]~33_combout ;
wire \X_ADDR[9]~34 ;
wire \X_ADDR[10]~35_combout ;
wire \X_ADDR[10]~36 ;
wire \X_ADDR[11]~37_combout ;
wire \X_ADDR[11]~38 ;
wire \X_ADDR[12]~39_combout ;
wire \X_ADDR[12]~40 ;
wire \X_ADDR[13]~41_combout ;
wire \Y_ADDR[0]~15_combout ;
wire \always0~0_combout ;
wire \Y_ADDR[0]~16 ;
wire \Y_ADDR[1]~17_combout ;
wire \Y_ADDR[1]~18 ;
wire \Y_ADDR[2]~19_combout ;
wire \Y_ADDR[2]~20 ;
wire \Y_ADDR[3]~21_combout ;
wire \Y_ADDR[3]~22 ;
wire \Y_ADDR[4]~23_combout ;
wire \Y_ADDR[4]~24 ;
wire \Y_ADDR[5]~25_combout ;
wire \Y_ADDR[5]~26 ;
wire \Y_ADDR[6]~27_combout ;
wire \Y_ADDR[6]~28 ;
wire \Y_ADDR[7]~29_combout ;
wire \Mult0|mult_core|romout[1][9]~0_combout ;
wire \Mult0|mult_core|romout[1][8]~1_combout ;
wire \Mult0|mult_core|_~0_combout ;
wire \Mult0|mult_core|romout[1][7]~2_combout ;
wire \Mult0|mult_core|romout[1][6]~3_combout ;
wire \Mult0|mult_core|romout[0][10]~4_combout ;
wire \Mult0|mult_core|romout[0][9]~6_combout ;
wire \Mult0|mult_core|romout[1][5]~5_combout ;
wire \Mult0|mult_core|romout[0][8]~7_combout ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ;
wire \Y_ADDR[7]~30 ;
wire \Y_ADDR[8]~31_combout ;
wire \Y_ADDR[8]~32 ;
wire \Y_ADDR[9]~33_combout ;
wire \Mult0|mult_core|romout[2][5]~combout ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ;
wire \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ;
wire \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ;
wire \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ;
wire \Mult0|mult_core|romout[0][7]~8_combout ;
wire \Mult0|mult_core|romout[0][6]~9_combout ;
wire \Mult0|mult_core|romout[0][5]~10_combout ;
wire \Add0~1 ;
wire \Add0~3 ;
wire \Add0~5 ;
wire \Add0~7 ;
wire \Add0~9 ;
wire \Add0~11 ;
wire \Add0~13 ;
wire \Add0~15 ;
wire \Add0~17 ;
wire \Add0~18_combout ;
wire \X_ADDR[13]~42 ;
wire \X_ADDR[14]~44_combout ;
wire \Y_ADDR[9]~34 ;
wire \Y_ADDR[10]~35_combout ;
wire \Mult0|mult_core|romout[2][6]~12_combout ;
wire \Mult0|mult_core|romout[1][10]~11_combout ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ;
wire \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ;
wire \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ;
wire \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ;
wire \Add0~19 ;
wire \Add0~20_combout ;
wire \W_EN~0_combout ;
wire \W_EN~feeder_combout ;
wire \W_EN~q ;
wire \mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ;
wire \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ;
wire \Mult1|mult_core|romout[1][10]~12_combout ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~11 ;
wire \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ;
wire \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ;
wire \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ;
wire \Add3~19 ;
wire \Add3~20_combout ;
wire \GPIO_1_D[27]~input_o ;
wire \pixel_data_RGB332[7]~feeder_combout ;
wire \Add0~0_combout ;
wire \Add0~2_combout ;
wire \Add0~4_combout ;
wire \Add0~6_combout ;
wire \Add0~8_combout ;
wire \Add0~10_combout ;
wire \Add0~12_combout ;
wire \Add0~14_combout ;
wire \Add0~16_combout ;
wire \Add3~0_combout ;
wire \Add3~2_combout ;
wire \Add3~4_combout ;
wire \Add3~6_combout ;
wire \Add3~8_combout ;
wire \Add3~10_combout ;
wire \Add3~12_combout ;
wire \Add3~14_combout ;
wire \Add3~16_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a7~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a15~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[7]~2_combout ;
wire \mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a23~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|decode2|w_anode329w[2]~0_combout ;
wire \GPIO_1_D[23]~input_o ;
wire \pixel_data_RGB332[0]~feeder_combout ;
wire \GPIO_1_D[24]~input_o ;
wire \pixel_data_RGB332[1]~feeder_combout ;
wire \GPIO_1_D[20]~input_o ;
wire \GPIO_1_D[21]~input_o ;
wire \GPIO_1_D[22]~input_o ;
wire \pixel_data_RGB332[4]~feeder_combout ;
wire \GPIO_1_D[25]~input_o ;
wire \GPIO_1_D[26]~input_o ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a31 ;
wire \driver|PIXEL_COLOR_OUT[7]~3_combout ;
wire \driver|PIXEL_COLOR_OUT[7]~0_combout ;
wire \LessThan0~0_combout ;
wire \driver|PIXEL_COLOR_OUT[7]~1_combout ;
wire \driver|PIXEL_COLOR_OUT[7]~4_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a14~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a6~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[6]~5_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a22~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a30 ;
wire \driver|PIXEL_COLOR_OUT[6]~6_combout ;
wire \driver|PIXEL_COLOR_OUT[6]~7_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a5~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a13~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[5]~8_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a21~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a29 ;
wire \driver|PIXEL_COLOR_OUT[5]~9_combout ;
wire \driver|PIXEL_COLOR_OUT[5]~10_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a20~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a28 ;
wire \driver|PIXEL_COLOR_OUT[4]~12_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a4~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a12~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[4]~11_combout ;
wire \driver|PIXEL_COLOR_OUT[4]~13_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a11~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a3~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[3]~14_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a19~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a27 ;
wire \driver|PIXEL_COLOR_OUT[3]~15_combout ;
wire \driver|PIXEL_COLOR_OUT[3]~16_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a26 ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a18~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[2]~18_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a10~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a2~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[2]~17_combout ;
wire \driver|PIXEL_COLOR_OUT[2]~19_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a1~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a9~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[1]~21_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a25 ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a17~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[1]~20_combout ;
wire \driver|PIXEL_COLOR_OUT[1]~22_combout ;
wire \driver|PIXEL_COLOR_OUT[1]~23_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a24~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a16~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[0]~24_combout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a8~portbdataout ;
wire \mem|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ;
wire \driver|PIXEL_COLOR_OUT[0]~25_combout ;
wire \driver|PIXEL_COLOR_OUT[0]~26_combout ;
wire \driver|PIXEL_COLOR_OUT[0]~27_combout ;
wire [2:0] \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w ;
wire [4:0] \PLL_inst|altpll_component|auto_generated|wire_pll1_clk ;
wire [14:0] Y_ADDR;
wire [9:0] \driver|line_count ;
wire [2:0] \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w ;
wire [7:0] pixel_data_RGB332;
wire [1:0] \mem|mem_rtl_0|auto_generated|address_reg_b ;
wire [9:0] \driver|pixel_count ;
wire [14:0] X_ADDR;
wire [2:0] \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode370w ;
wire [2:0] \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w ;

wire [4:0] \PLL_inst|altpll_component|auto_generated|pll1_CLK_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a23_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a22_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a21_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a20_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a19_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a18_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a17_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus ;
wire [8:0] \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a16_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus ;
wire [0:0] \mem|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;

assign \PLL_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \PLL_inst|altpll_component|auto_generated|pll1_CLK_bus [0];
assign \PLL_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \PLL_inst|altpll_component|auto_generated|pll1_CLK_bus [1];
assign \PLL_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \PLL_inst|altpll_component|auto_generated|pll1_CLK_bus [2];
assign \PLL_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \PLL_inst|altpll_component|auto_generated|pll1_CLK_bus [3];
assign \PLL_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \PLL_inst|altpll_component|auto_generated|pll1_CLK_bus [4];

assign \mem|mem_rtl_0|auto_generated|ram_block1a15~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a7~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a23~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a23_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a14~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a6~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a22~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a22_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a13~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a5~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a21~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a21_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a12~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a4~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a20~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a20_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a11~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a3~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a19~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a19_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a10~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a2~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a18~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a18_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a17~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a17_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a9~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a1~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a24~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus [0];
assign \mem|mem_rtl_0|auto_generated|ram_block1a25  = \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus [1];
assign \mem|mem_rtl_0|auto_generated|ram_block1a26  = \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus [2];
assign \mem|mem_rtl_0|auto_generated|ram_block1a27  = \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus [3];
assign \mem|mem_rtl_0|auto_generated|ram_block1a28  = \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus [4];
assign \mem|mem_rtl_0|auto_generated|ram_block1a29  = \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus [5];
assign \mem|mem_rtl_0|auto_generated|ram_block1a30  = \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus [6];
assign \mem|mem_rtl_0|auto_generated|ram_block1a31  = \mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus [7];

assign \mem|mem_rtl_0|auto_generated|ram_block1a16~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a16_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a8~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0];

assign \mem|mem_rtl_0|auto_generated|ram_block1a0~portbdataout  = \mem|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];

// Location: IOOBUF_X1_Y34_N9
cycloneive_io_obuf \GPIO_0_D[0]~output (
	.i(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[0]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[0]~output .bus_hold = "false";
defparam \GPIO_0_D[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X1_Y34_N2
cycloneive_io_obuf \GPIO_0_D[1]~output (
	.i(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[1]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[1]~output .bus_hold = "false";
defparam \GPIO_0_D[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X7_Y34_N9
cycloneive_io_obuf \GPIO_0_D[2]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[2]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[2]~output .bus_hold = "false";
defparam \GPIO_0_D[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X7_Y34_N16
cycloneive_io_obuf \GPIO_0_D[3]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[3]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[3]~output .bus_hold = "false";
defparam \GPIO_0_D[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X3_Y34_N2
cycloneive_io_obuf \GPIO_0_D[4]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[4]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[4]~output .bus_hold = "false";
defparam \GPIO_0_D[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X7_Y34_N2
cycloneive_io_obuf \GPIO_0_D[5]~output (
	.i(\driver|V_SYNC_NEG~2_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[5]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[5]~output .bus_hold = "false";
defparam \GPIO_0_D[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X9_Y34_N23
cycloneive_io_obuf \GPIO_0_D[6]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[6]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[6]~output .bus_hold = "false";
defparam \GPIO_0_D[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X11_Y34_N2
cycloneive_io_obuf \GPIO_0_D[7]~output (
	.i(\driver|H_SYNC_NEG~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[7]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[7]~output .bus_hold = "false";
defparam \GPIO_0_D[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y34_N23
cycloneive_io_obuf \GPIO_0_D[8]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[8]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[8]~output .bus_hold = "false";
defparam \GPIO_0_D[8]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X5_Y34_N16
cycloneive_io_obuf \GPIO_0_D[9]~output (
	.i(\driver|PIXEL_COLOR_OUT[7]~4_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[9]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[9]~output .bus_hold = "false";
defparam \GPIO_0_D[9]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X16_Y34_N9
cycloneive_io_obuf \GPIO_0_D[10]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[10]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[10]~output .bus_hold = "false";
defparam \GPIO_0_D[10]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X16_Y34_N2
cycloneive_io_obuf \GPIO_0_D[11]~output (
	.i(\driver|PIXEL_COLOR_OUT[6]~7_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[11]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[11]~output .bus_hold = "false";
defparam \GPIO_0_D[11]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X18_Y34_N2
cycloneive_io_obuf \GPIO_0_D[12]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[12]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[12]~output .bus_hold = "false";
defparam \GPIO_0_D[12]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X9_Y34_N9
cycloneive_io_obuf \GPIO_0_D[13]~output (
	.i(\driver|PIXEL_COLOR_OUT[5]~10_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[13]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[13]~output .bus_hold = "false";
defparam \GPIO_0_D[13]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X20_Y34_N23
cycloneive_io_obuf \GPIO_0_D[14]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[14]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[14]~output .bus_hold = "false";
defparam \GPIO_0_D[14]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X18_Y34_N23
cycloneive_io_obuf \GPIO_0_D[15]~output (
	.i(\driver|PIXEL_COLOR_OUT[4]~13_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[15]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[15]~output .bus_hold = "false";
defparam \GPIO_0_D[15]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X23_Y34_N16
cycloneive_io_obuf \GPIO_0_D[16]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[16]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[16]~output .bus_hold = "false";
defparam \GPIO_0_D[16]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X14_Y34_N16
cycloneive_io_obuf \GPIO_0_D[17]~output (
	.i(\driver|PIXEL_COLOR_OUT[3]~16_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[17]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[17]~output .bus_hold = "false";
defparam \GPIO_0_D[17]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X16_Y34_N16
cycloneive_io_obuf \GPIO_0_D[18]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[18]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[18]~output .bus_hold = "false";
defparam \GPIO_0_D[18]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X23_Y34_N23
cycloneive_io_obuf \GPIO_0_D[19]~output (
	.i(\driver|PIXEL_COLOR_OUT[2]~19_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[19]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[19]~output .bus_hold = "false";
defparam \GPIO_0_D[19]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X20_Y34_N9
cycloneive_io_obuf \GPIO_0_D[20]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[20]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[20]~output .bus_hold = "false";
defparam \GPIO_0_D[20]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X20_Y34_N16
cycloneive_io_obuf \GPIO_0_D[21]~output (
	.i(\driver|PIXEL_COLOR_OUT[1]~23_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[21]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[21]~output .bus_hold = "false";
defparam \GPIO_0_D[21]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X34_Y34_N2
cycloneive_io_obuf \GPIO_0_D[22]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[22]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[22]~output .bus_hold = "false";
defparam \GPIO_0_D[22]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X29_Y34_N16
cycloneive_io_obuf \GPIO_0_D[23]~output (
	.i(\driver|PIXEL_COLOR_OUT[0]~27_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[23]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[23]~output .bus_hold = "false";
defparam \GPIO_0_D[23]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X31_Y34_N2
cycloneive_io_obuf \GPIO_0_D[24]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[24]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[24]~output .bus_hold = "false";
defparam \GPIO_0_D[24]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X31_Y34_N9
cycloneive_io_obuf \GPIO_0_D[25]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[25]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[25]~output .bus_hold = "false";
defparam \GPIO_0_D[25]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X45_Y34_N9
cycloneive_io_obuf \GPIO_0_D[26]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[26]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[26]~output .bus_hold = "false";
defparam \GPIO_0_D[26]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X45_Y34_N16
cycloneive_io_obuf \GPIO_0_D[27]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[27]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[27]~output .bus_hold = "false";
defparam \GPIO_0_D[27]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X38_Y34_N2
cycloneive_io_obuf \GPIO_0_D[28]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[28]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[28]~output .bus_hold = "false";
defparam \GPIO_0_D[28]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X40_Y34_N9
cycloneive_io_obuf \GPIO_0_D[29]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[29]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[29]~output .bus_hold = "false";
defparam \GPIO_0_D[29]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X43_Y34_N16
cycloneive_io_obuf \GPIO_0_D[30]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[30]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[30]~output .bus_hold = "false";
defparam \GPIO_0_D[30]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X51_Y34_N16
cycloneive_io_obuf \GPIO_0_D[31]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[31]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[31]~output .bus_hold = "false";
defparam \GPIO_0_D[31]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X51_Y34_N23
cycloneive_io_obuf \GPIO_0_D[32]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[32]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[32]~output .bus_hold = "false";
defparam \GPIO_0_D[32]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X43_Y34_N23
cycloneive_io_obuf \GPIO_0_D[33]~output (
	.i(gnd),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(GPIO_0_D[33]),
	.obar());
// synopsys translate_off
defparam \GPIO_0_D[33]~output .bus_hold = "false";
defparam \GPIO_0_D[33]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X27_Y0_N22
cycloneive_io_ibuf \CLOCK_50~input (
	.i(CLOCK_50),
	.ibar(gnd),
	.o(\CLOCK_50~input_o ));
// synopsys translate_off
defparam \CLOCK_50~input .bus_hold = "false";
defparam \CLOCK_50~input .simulate_z_as = "z";
// synopsys translate_on

// Location: PLL_4
cycloneive_pll \PLL_inst|altpll_component|auto_generated|pll1 (
	.areset(gnd),
	.pfdena(vcc),
	.fbin(\PLL_inst|altpll_component|auto_generated|wire_pll1_fbout ),
	.phaseupdown(gnd),
	.phasestep(gnd),
	.scandata(gnd),
	.scanclk(gnd),
	.scanclkena(vcc),
	.configupdate(gnd),
	.clkswitch(gnd),
	.inclk({gnd,\CLOCK_50~input_o }),
	.phasecounterselect(3'b000),
	.phasedone(),
	.scandataout(),
	.scandone(),
	.activeclock(),
	.locked(),
	.vcooverrange(),
	.vcounderrange(),
	.fbout(\PLL_inst|altpll_component|auto_generated|wire_pll1_fbout ),
	.clk(\PLL_inst|altpll_component|auto_generated|pll1_CLK_bus ),
	.clkbad());
// synopsys translate_off
defparam \PLL_inst|altpll_component|auto_generated|pll1 .auto_settings = "false";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c0_high = 13;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c0_initial = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c0_low = 12;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c0_mode = "odd";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c0_ph = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c1_high = 12;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c1_initial = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c1_low = 12;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c1_mode = "even";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c1_ph = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c2_high = 6;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c2_initial = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c2_low = 6;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c2_mode = "even";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c2_ph = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c3_high = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c3_initial = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c3_low = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c3_ph = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c4_high = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c4_initial = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c4_low = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c4_ph = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 25;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 12;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 2;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk2_counter = "c2";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .m = 12;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .m_initial = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .m_ph = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .n = 1;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .vco_center = 1538;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto";
defparam \PLL_inst|altpll_component|auto_generated|pll1 .vco_max = 3333;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .vco_min = 1538;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208;
defparam \PLL_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2;
// synopsys translate_on

// Location: CLKCTRL_G18
cycloneive_clkctrl \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl (
	.ena(vcc),
	.inclk({vcc,vcc,vcc,\PLL_inst|altpll_component|auto_generated|wire_pll1_clk [0]}),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ));
// synopsys translate_off
defparam \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock";
defparam \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none";
// synopsys translate_on

// Location: CLKCTRL_G19
cycloneive_clkctrl \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl (
	.ena(vcc),
	.inclk({vcc,vcc,vcc,\PLL_inst|altpll_component|auto_generated|wire_pll1_clk [1]}),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ));
// synopsys translate_off
defparam \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock";
defparam \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N12
cycloneive_lcell_comb \driver|line_count[0]~10 (
// Equation(s):
// \driver|line_count[0]~10_combout  = \driver|line_count [0] $ (VCC)
// \driver|line_count[0]~11  = CARRY(\driver|line_count [0])

	.dataa(\driver|line_count [0]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\driver|line_count[0]~10_combout ),
	.cout(\driver|line_count[0]~11 ));
// synopsys translate_off
defparam \driver|line_count[0]~10 .lut_mask = 16'h55AA;
defparam \driver|line_count[0]~10 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N14
cycloneive_lcell_comb \driver|line_count[1]~12 (
// Equation(s):
// \driver|line_count[1]~12_combout  = (\driver|line_count [1] & (!\driver|line_count[0]~11 )) # (!\driver|line_count [1] & ((\driver|line_count[0]~11 ) # (GND)))
// \driver|line_count[1]~13  = CARRY((!\driver|line_count[0]~11 ) # (!\driver|line_count [1]))

	.dataa(gnd),
	.datab(\driver|line_count [1]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|line_count[0]~11 ),
	.combout(\driver|line_count[1]~12_combout ),
	.cout(\driver|line_count[1]~13 ));
// synopsys translate_off
defparam \driver|line_count[1]~12 .lut_mask = 16'h3C3F;
defparam \driver|line_count[1]~12 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N16
cycloneive_lcell_comb \driver|line_count[2]~14 (
// Equation(s):
// \driver|line_count[2]~14_combout  = (\driver|line_count [2] & (\driver|line_count[1]~13  $ (GND))) # (!\driver|line_count [2] & (!\driver|line_count[1]~13  & VCC))
// \driver|line_count[2]~15  = CARRY((\driver|line_count [2] & !\driver|line_count[1]~13 ))

	.dataa(gnd),
	.datab(\driver|line_count [2]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|line_count[1]~13 ),
	.combout(\driver|line_count[2]~14_combout ),
	.cout(\driver|line_count[2]~15 ));
// synopsys translate_off
defparam \driver|line_count[2]~14 .lut_mask = 16'hC30C;
defparam \driver|line_count[2]~14 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N8
cycloneive_lcell_comb \driver|pixel_count[0]~10 (
// Equation(s):
// \driver|pixel_count[0]~10_combout  = \driver|pixel_count [0] $ (VCC)
// \driver|pixel_count[0]~11  = CARRY(\driver|pixel_count [0])

	.dataa(gnd),
	.datab(\driver|pixel_count [0]),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\driver|pixel_count[0]~10_combout ),
	.cout(\driver|pixel_count[0]~11 ));
// synopsys translate_off
defparam \driver|pixel_count[0]~10 .lut_mask = 16'h33CC;
defparam \driver|pixel_count[0]~10 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X28_Y13_N9
dffeas \driver|pixel_count[0] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[0]~10_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [0]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[0] .is_wysiwyg = "true";
defparam \driver|pixel_count[0] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N10
cycloneive_lcell_comb \driver|pixel_count[1]~12 (
// Equation(s):
// \driver|pixel_count[1]~12_combout  = (\driver|pixel_count [1] & (!\driver|pixel_count[0]~11 )) # (!\driver|pixel_count [1] & ((\driver|pixel_count[0]~11 ) # (GND)))
// \driver|pixel_count[1]~13  = CARRY((!\driver|pixel_count[0]~11 ) # (!\driver|pixel_count [1]))

	.dataa(\driver|pixel_count [1]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|pixel_count[0]~11 ),
	.combout(\driver|pixel_count[1]~12_combout ),
	.cout(\driver|pixel_count[1]~13 ));
// synopsys translate_off
defparam \driver|pixel_count[1]~12 .lut_mask = 16'h5A5F;
defparam \driver|pixel_count[1]~12 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N11
dffeas \driver|pixel_count[1] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[1]~12_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [1]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[1] .is_wysiwyg = "true";
defparam \driver|pixel_count[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N12
cycloneive_lcell_comb \driver|pixel_count[2]~14 (
// Equation(s):
// \driver|pixel_count[2]~14_combout  = (\driver|pixel_count [2] & (\driver|pixel_count[1]~13  $ (GND))) # (!\driver|pixel_count [2] & (!\driver|pixel_count[1]~13  & VCC))
// \driver|pixel_count[2]~15  = CARRY((\driver|pixel_count [2] & !\driver|pixel_count[1]~13 ))

	.dataa(\driver|pixel_count [2]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|pixel_count[1]~13 ),
	.combout(\driver|pixel_count[2]~14_combout ),
	.cout(\driver|pixel_count[2]~15 ));
// synopsys translate_off
defparam \driver|pixel_count[2]~14 .lut_mask = 16'hA50A;
defparam \driver|pixel_count[2]~14 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N13
dffeas \driver|pixel_count[2] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[2]~14_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [2]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[2] .is_wysiwyg = "true";
defparam \driver|pixel_count[2] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N14
cycloneive_lcell_comb \driver|pixel_count[3]~16 (
// Equation(s):
// \driver|pixel_count[3]~16_combout  = (\driver|pixel_count [3] & (!\driver|pixel_count[2]~15 )) # (!\driver|pixel_count [3] & ((\driver|pixel_count[2]~15 ) # (GND)))
// \driver|pixel_count[3]~17  = CARRY((!\driver|pixel_count[2]~15 ) # (!\driver|pixel_count [3]))

	.dataa(gnd),
	.datab(\driver|pixel_count [3]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|pixel_count[2]~15 ),
	.combout(\driver|pixel_count[3]~16_combout ),
	.cout(\driver|pixel_count[3]~17 ));
// synopsys translate_off
defparam \driver|pixel_count[3]~16 .lut_mask = 16'h3C3F;
defparam \driver|pixel_count[3]~16 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N15
dffeas \driver|pixel_count[3] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[3]~16_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [3]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[3] .is_wysiwyg = "true";
defparam \driver|pixel_count[3] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N16
cycloneive_lcell_comb \driver|pixel_count[4]~18 (
// Equation(s):
// \driver|pixel_count[4]~18_combout  = (\driver|pixel_count [4] & (\driver|pixel_count[3]~17  $ (GND))) # (!\driver|pixel_count [4] & (!\driver|pixel_count[3]~17  & VCC))
// \driver|pixel_count[4]~19  = CARRY((\driver|pixel_count [4] & !\driver|pixel_count[3]~17 ))

	.dataa(\driver|pixel_count [4]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|pixel_count[3]~17 ),
	.combout(\driver|pixel_count[4]~18_combout ),
	.cout(\driver|pixel_count[4]~19 ));
// synopsys translate_off
defparam \driver|pixel_count[4]~18 .lut_mask = 16'hA50A;
defparam \driver|pixel_count[4]~18 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N17
dffeas \driver|pixel_count[4] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[4]~18_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [4]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[4] .is_wysiwyg = "true";
defparam \driver|pixel_count[4] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N18
cycloneive_lcell_comb \driver|pixel_count[5]~20 (
// Equation(s):
// \driver|pixel_count[5]~20_combout  = (\driver|pixel_count [5] & (!\driver|pixel_count[4]~19 )) # (!\driver|pixel_count [5] & ((\driver|pixel_count[4]~19 ) # (GND)))
// \driver|pixel_count[5]~21  = CARRY((!\driver|pixel_count[4]~19 ) # (!\driver|pixel_count [5]))

	.dataa(gnd),
	.datab(\driver|pixel_count [5]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|pixel_count[4]~19 ),
	.combout(\driver|pixel_count[5]~20_combout ),
	.cout(\driver|pixel_count[5]~21 ));
// synopsys translate_off
defparam \driver|pixel_count[5]~20 .lut_mask = 16'h3C3F;
defparam \driver|pixel_count[5]~20 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N19
dffeas \driver|pixel_count[5] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[5]~20_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [5]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[5] .is_wysiwyg = "true";
defparam \driver|pixel_count[5] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N20
cycloneive_lcell_comb \driver|pixel_count[6]~22 (
// Equation(s):
// \driver|pixel_count[6]~22_combout  = (\driver|pixel_count [6] & (\driver|pixel_count[5]~21  $ (GND))) # (!\driver|pixel_count [6] & (!\driver|pixel_count[5]~21  & VCC))
// \driver|pixel_count[6]~23  = CARRY((\driver|pixel_count [6] & !\driver|pixel_count[5]~21 ))

	.dataa(gnd),
	.datab(\driver|pixel_count [6]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|pixel_count[5]~21 ),
	.combout(\driver|pixel_count[6]~22_combout ),
	.cout(\driver|pixel_count[6]~23 ));
// synopsys translate_off
defparam \driver|pixel_count[6]~22 .lut_mask = 16'hC30C;
defparam \driver|pixel_count[6]~22 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N21
dffeas \driver|pixel_count[6] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[6]~22_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [6]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[6] .is_wysiwyg = "true";
defparam \driver|pixel_count[6] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N22
cycloneive_lcell_comb \driver|pixel_count[7]~24 (
// Equation(s):
// \driver|pixel_count[7]~24_combout  = (\driver|pixel_count [7] & (!\driver|pixel_count[6]~23 )) # (!\driver|pixel_count [7] & ((\driver|pixel_count[6]~23 ) # (GND)))
// \driver|pixel_count[7]~25  = CARRY((!\driver|pixel_count[6]~23 ) # (!\driver|pixel_count [7]))

	.dataa(\driver|pixel_count [7]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|pixel_count[6]~23 ),
	.combout(\driver|pixel_count[7]~24_combout ),
	.cout(\driver|pixel_count[7]~25 ));
// synopsys translate_off
defparam \driver|pixel_count[7]~24 .lut_mask = 16'h5A5F;
defparam \driver|pixel_count[7]~24 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N23
dffeas \driver|pixel_count[7] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[7]~24_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [7]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[7] .is_wysiwyg = "true";
defparam \driver|pixel_count[7] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N24
cycloneive_lcell_comb \driver|pixel_count[8]~26 (
// Equation(s):
// \driver|pixel_count[8]~26_combout  = (\driver|pixel_count [8] & (\driver|pixel_count[7]~25  $ (GND))) # (!\driver|pixel_count [8] & (!\driver|pixel_count[7]~25  & VCC))
// \driver|pixel_count[8]~27  = CARRY((\driver|pixel_count [8] & !\driver|pixel_count[7]~25 ))

	.dataa(\driver|pixel_count [8]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|pixel_count[7]~25 ),
	.combout(\driver|pixel_count[8]~26_combout ),
	.cout(\driver|pixel_count[8]~27 ));
// synopsys translate_off
defparam \driver|pixel_count[8]~26 .lut_mask = 16'hA50A;
defparam \driver|pixel_count[8]~26 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N25
dffeas \driver|pixel_count[8] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[8]~26_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [8]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[8] .is_wysiwyg = "true";
defparam \driver|pixel_count[8] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N26
cycloneive_lcell_comb \driver|pixel_count[9]~28 (
// Equation(s):
// \driver|pixel_count[9]~28_combout  = \driver|pixel_count [9] $ (\driver|pixel_count[8]~27 )

	.dataa(\driver|pixel_count [9]),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(\driver|pixel_count[8]~27 ),
	.combout(\driver|pixel_count[9]~28_combout ),
	.cout());
// synopsys translate_off
defparam \driver|pixel_count[9]~28 .lut_mask = 16'h5A5A;
defparam \driver|pixel_count[9]~28 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y13_N27
dffeas \driver|pixel_count[9] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|pixel_count[9]~28_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~17_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|pixel_count [9]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|pixel_count[9] .is_wysiwyg = "true";
defparam \driver|pixel_count[9] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N6
cycloneive_lcell_comb \driver|Equal0~1 (
// Equation(s):
// \driver|Equal0~1_combout  = ((\driver|pixel_count [0]) # ((!\driver|pixel_count [1]) # (!\driver|pixel_count [9]))) # (!\driver|pixel_count [8])

	.dataa(\driver|pixel_count [8]),
	.datab(\driver|pixel_count [0]),
	.datac(\driver|pixel_count [9]),
	.datad(\driver|pixel_count [1]),
	.cin(gnd),
	.combout(\driver|Equal0~1_combout ),
	.cout());
// synopsys translate_off
defparam \driver|Equal0~1 .lut_mask = 16'hDFFF;
defparam \driver|Equal0~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N28
cycloneive_lcell_comb \driver|Equal0~2 (
// Equation(s):
// \driver|Equal0~2_combout  = (\driver|pixel_count [2]) # (!\driver|pixel_count [3])

	.dataa(gnd),
	.datab(gnd),
	.datac(\driver|pixel_count [3]),
	.datad(\driver|pixel_count [2]),
	.cin(gnd),
	.combout(\driver|Equal0~2_combout ),
	.cout());
// synopsys translate_off
defparam \driver|Equal0~2 .lut_mask = 16'hFF0F;
defparam \driver|Equal0~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N4
cycloneive_lcell_comb \driver|Equal0~0 (
// Equation(s):
// \driver|Equal0~0_combout  = ((\driver|pixel_count [5]) # ((\driver|pixel_count [7]) # (\driver|pixel_count [6]))) # (!\driver|pixel_count [4])

	.dataa(\driver|pixel_count [4]),
	.datab(\driver|pixel_count [5]),
	.datac(\driver|pixel_count [7]),
	.datad(\driver|pixel_count [6]),
	.cin(gnd),
	.combout(\driver|Equal0~0_combout ),
	.cout());
// synopsys translate_off
defparam \driver|Equal0~0 .lut_mask = 16'hFFFD;
defparam \driver|Equal0~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X53_Y14_N1
cycloneive_io_ibuf \KEY[0]~input (
	.i(KEY[0]),
	.ibar(gnd),
	.o(\KEY[0]~input_o ));
// synopsys translate_off
defparam \KEY[0]~input .bus_hold = "false";
defparam \KEY[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N30
cycloneive_lcell_comb \driver|line_count[9]~17 (
// Equation(s):
// \driver|line_count[9]~17_combout  = ((!\driver|Equal0~1_combout  & (!\driver|Equal0~2_combout  & !\driver|Equal0~0_combout ))) # (!\KEY[0]~input_o )

	.dataa(\driver|Equal0~1_combout ),
	.datab(\driver|Equal0~2_combout ),
	.datac(\driver|Equal0~0_combout ),
	.datad(\KEY[0]~input_o ),
	.cin(gnd),
	.combout(\driver|line_count[9]~17_combout ),
	.cout());
// synopsys translate_off
defparam \driver|line_count[9]~17 .lut_mask = 16'h01FF;
defparam \driver|line_count[9]~17 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X30_Y10_N17
dffeas \driver|line_count[2] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[2]~14_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [2]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[2] .is_wysiwyg = "true";
defparam \driver|line_count[2] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N18
cycloneive_lcell_comb \driver|line_count[3]~18 (
// Equation(s):
// \driver|line_count[3]~18_combout  = (\driver|line_count [3] & (!\driver|line_count[2]~15 )) # (!\driver|line_count [3] & ((\driver|line_count[2]~15 ) # (GND)))
// \driver|line_count[3]~19  = CARRY((!\driver|line_count[2]~15 ) # (!\driver|line_count [3]))

	.dataa(gnd),
	.datab(\driver|line_count [3]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|line_count[2]~15 ),
	.combout(\driver|line_count[3]~18_combout ),
	.cout(\driver|line_count[3]~19 ));
// synopsys translate_off
defparam \driver|line_count[3]~18 .lut_mask = 16'h3C3F;
defparam \driver|line_count[3]~18 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y10_N19
dffeas \driver|line_count[3] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[3]~18_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [3]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[3] .is_wysiwyg = "true";
defparam \driver|line_count[3] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N20
cycloneive_lcell_comb \driver|line_count[4]~20 (
// Equation(s):
// \driver|line_count[4]~20_combout  = (\driver|line_count [4] & (\driver|line_count[3]~19  $ (GND))) # (!\driver|line_count [4] & (!\driver|line_count[3]~19  & VCC))
// \driver|line_count[4]~21  = CARRY((\driver|line_count [4] & !\driver|line_count[3]~19 ))

	.dataa(gnd),
	.datab(\driver|line_count [4]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|line_count[3]~19 ),
	.combout(\driver|line_count[4]~20_combout ),
	.cout(\driver|line_count[4]~21 ));
// synopsys translate_off
defparam \driver|line_count[4]~20 .lut_mask = 16'hC30C;
defparam \driver|line_count[4]~20 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y10_N21
dffeas \driver|line_count[4] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[4]~20_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [4]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[4] .is_wysiwyg = "true";
defparam \driver|line_count[4] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N22
cycloneive_lcell_comb \driver|line_count[5]~22 (
// Equation(s):
// \driver|line_count[5]~22_combout  = (\driver|line_count [5] & (!\driver|line_count[4]~21 )) # (!\driver|line_count [5] & ((\driver|line_count[4]~21 ) # (GND)))
// \driver|line_count[5]~23  = CARRY((!\driver|line_count[4]~21 ) # (!\driver|line_count [5]))

	.dataa(\driver|line_count [5]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|line_count[4]~21 ),
	.combout(\driver|line_count[5]~22_combout ),
	.cout(\driver|line_count[5]~23 ));
// synopsys translate_off
defparam \driver|line_count[5]~22 .lut_mask = 16'h5A5F;
defparam \driver|line_count[5]~22 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y10_N23
dffeas \driver|line_count[5] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[5]~22_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [5]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[5] .is_wysiwyg = "true";
defparam \driver|line_count[5] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N24
cycloneive_lcell_comb \driver|line_count[6]~24 (
// Equation(s):
// \driver|line_count[6]~24_combout  = (\driver|line_count [6] & (\driver|line_count[5]~23  $ (GND))) # (!\driver|line_count [6] & (!\driver|line_count[5]~23  & VCC))
// \driver|line_count[6]~25  = CARRY((\driver|line_count [6] & !\driver|line_count[5]~23 ))

	.dataa(gnd),
	.datab(\driver|line_count [6]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|line_count[5]~23 ),
	.combout(\driver|line_count[6]~24_combout ),
	.cout(\driver|line_count[6]~25 ));
// synopsys translate_off
defparam \driver|line_count[6]~24 .lut_mask = 16'hC30C;
defparam \driver|line_count[6]~24 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y10_N25
dffeas \driver|line_count[6] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[6]~24_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [6]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[6] .is_wysiwyg = "true";
defparam \driver|line_count[6] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N26
cycloneive_lcell_comb \driver|line_count[7]~26 (
// Equation(s):
// \driver|line_count[7]~26_combout  = (\driver|line_count [7] & (!\driver|line_count[6]~25 )) # (!\driver|line_count [7] & ((\driver|line_count[6]~25 ) # (GND)))
// \driver|line_count[7]~27  = CARRY((!\driver|line_count[6]~25 ) # (!\driver|line_count [7]))

	.dataa(\driver|line_count [7]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|line_count[6]~25 ),
	.combout(\driver|line_count[7]~26_combout ),
	.cout(\driver|line_count[7]~27 ));
// synopsys translate_off
defparam \driver|line_count[7]~26 .lut_mask = 16'h5A5F;
defparam \driver|line_count[7]~26 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y10_N27
dffeas \driver|line_count[7] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[7]~26_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [7]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[7] .is_wysiwyg = "true";
defparam \driver|line_count[7] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N28
cycloneive_lcell_comb \driver|line_count[8]~28 (
// Equation(s):
// \driver|line_count[8]~28_combout  = (\driver|line_count [8] & (\driver|line_count[7]~27  $ (GND))) # (!\driver|line_count [8] & (!\driver|line_count[7]~27  & VCC))
// \driver|line_count[8]~29  = CARRY((\driver|line_count [8] & !\driver|line_count[7]~27 ))

	.dataa(gnd),
	.datab(\driver|line_count [8]),
	.datac(gnd),
	.datad(vcc),
	.cin(\driver|line_count[7]~27 ),
	.combout(\driver|line_count[8]~28_combout ),
	.cout(\driver|line_count[8]~29 ));
// synopsys translate_off
defparam \driver|line_count[8]~28 .lut_mask = 16'hC30C;
defparam \driver|line_count[8]~28 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y10_N29
dffeas \driver|line_count[8] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[8]~28_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [8]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[8] .is_wysiwyg = "true";
defparam \driver|line_count[8] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N30
cycloneive_lcell_comb \driver|line_count[9]~30 (
// Equation(s):
// \driver|line_count[9]~30_combout  = \driver|line_count [9] $ (\driver|line_count[8]~29 )

	.dataa(\driver|line_count [9]),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(\driver|line_count[8]~29 ),
	.combout(\driver|line_count[9]~30_combout ),
	.cout());
// synopsys translate_off
defparam \driver|line_count[9]~30 .lut_mask = 16'h5A5A;
defparam \driver|line_count[9]~30 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y10_N31
dffeas \driver|line_count[9] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[9]~30_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [9]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[9] .is_wysiwyg = "true";
defparam \driver|line_count[9] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N8
cycloneive_lcell_comb \Mult1|mult_core|_~1 (
// Equation(s):
// \Mult1|mult_core|_~1_combout  = (\driver|line_count [9] & !\driver|line_count [8])

	.dataa(gnd),
	.datab(gnd),
	.datac(\driver|line_count [9]),
	.datad(\driver|line_count [8]),
	.cin(gnd),
	.combout(\Mult1|mult_core|_~1_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|_~1 .lut_mask = 16'h00F0;
defparam \Mult1|mult_core|_~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N24
cycloneive_lcell_comb \driver|Equal1~0 (
// Equation(s):
// \driver|Equal1~0_combout  = (!\driver|line_count [4] & (!\driver|line_count [5] & !\driver|line_count [6]))

	.dataa(gnd),
	.datab(\driver|line_count [4]),
	.datac(\driver|line_count [5]),
	.datad(\driver|line_count [6]),
	.cin(gnd),
	.combout(\driver|Equal1~0_combout ),
	.cout());
// synopsys translate_off
defparam \driver|Equal1~0 .lut_mask = 16'h0003;
defparam \driver|Equal1~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N20
cycloneive_lcell_comb \driver|Equal1~1 (
// Equation(s):
// \driver|Equal1~1_combout  = ((\driver|line_count [0]) # ((\driver|line_count [7]) # (!\driver|Equal1~0_combout ))) # (!\driver|line_count [3])

	.dataa(\driver|line_count [3]),
	.datab(\driver|line_count [0]),
	.datac(\driver|line_count [7]),
	.datad(\driver|Equal1~0_combout ),
	.cin(gnd),
	.combout(\driver|Equal1~1_combout ),
	.cout());
// synopsys translate_off
defparam \driver|Equal1~1 .lut_mask = 16'hFDFF;
defparam \driver|Equal1~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N14
cycloneive_lcell_comb \Mult1|mult_core|_~0 (
// Equation(s):
// \Mult1|mult_core|_~0_combout  = (!\driver|line_count [1] & \driver|line_count [2])

	.dataa(\driver|line_count [1]),
	.datab(gnd),
	.datac(gnd),
	.datad(\driver|line_count [2]),
	.cin(gnd),
	.combout(\Mult1|mult_core|_~0_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|_~0 .lut_mask = 16'h5500;
defparam \Mult1|mult_core|_~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N18
cycloneive_lcell_comb \driver|line_count[9]~16 (
// Equation(s):
// \driver|line_count[9]~16_combout  = ((\Mult1|mult_core|_~1_combout  & (!\driver|Equal1~1_combout  & \Mult1|mult_core|_~0_combout ))) # (!\KEY[0]~input_o )

	.dataa(\Mult1|mult_core|_~1_combout ),
	.datab(\driver|Equal1~1_combout ),
	.datac(\Mult1|mult_core|_~0_combout ),
	.datad(\KEY[0]~input_o ),
	.cin(gnd),
	.combout(\driver|line_count[9]~16_combout ),
	.cout());
// synopsys translate_off
defparam \driver|line_count[9]~16 .lut_mask = 16'h20FF;
defparam \driver|line_count[9]~16 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X30_Y10_N13
dffeas \driver|line_count[0] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[0]~10_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [0]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[0] .is_wysiwyg = "true";
defparam \driver|line_count[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y10_N15
dffeas \driver|line_count[1] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\driver|line_count[1]~12_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\driver|line_count[9]~16_combout ),
	.sload(gnd),
	.ena(\driver|line_count[9]~17_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\driver|line_count [1]),
	.prn(vcc));
// synopsys translate_off
defparam \driver|line_count[1] .is_wysiwyg = "true";
defparam \driver|line_count[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N10
cycloneive_lcell_comb \driver|V_SYNC_NEG~1 (
// Equation(s):
// \driver|V_SYNC_NEG~1_combout  = (((!\driver|line_count [6]) # (!\driver|line_count [7])) # (!\driver|line_count [8])) # (!\driver|line_count [1])

	.dataa(\driver|line_count [1]),
	.datab(\driver|line_count [8]),
	.datac(\driver|line_count [7]),
	.datad(\driver|line_count [6]),
	.cin(gnd),
	.combout(\driver|V_SYNC_NEG~1_combout ),
	.cout());
// synopsys translate_off
defparam \driver|V_SYNC_NEG~1 .lut_mask = 16'h7FFF;
defparam \driver|V_SYNC_NEG~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N16
cycloneive_lcell_comb \driver|V_SYNC_NEG~0 (
// Equation(s):
// \driver|V_SYNC_NEG~0_combout  = ((\driver|line_count [4]) # ((\driver|line_count [2]) # (!\driver|line_count [5]))) # (!\driver|line_count [3])

	.dataa(\driver|line_count [3]),
	.datab(\driver|line_count [4]),
	.datac(\driver|line_count [5]),
	.datad(\driver|line_count [2]),
	.cin(gnd),
	.combout(\driver|V_SYNC_NEG~0_combout ),
	.cout());
// synopsys translate_off
defparam \driver|V_SYNC_NEG~0 .lut_mask = 16'hFFDF;
defparam \driver|V_SYNC_NEG~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N28
cycloneive_lcell_comb \driver|V_SYNC_NEG~2 (
// Equation(s):
// \driver|V_SYNC_NEG~2_combout  = (\driver|V_SYNC_NEG~1_combout ) # ((\driver|V_SYNC_NEG~0_combout ) # (\driver|line_count [9]))

	.dataa(\driver|V_SYNC_NEG~1_combout ),
	.datab(\driver|V_SYNC_NEG~0_combout ),
	.datac(\driver|line_count [9]),
	.datad(gnd),
	.cin(gnd),
	.combout(\driver|V_SYNC_NEG~2_combout ),
	.cout());
// synopsys translate_off
defparam \driver|V_SYNC_NEG~2 .lut_mask = 16'hFEFE;
defparam \driver|V_SYNC_NEG~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N0
cycloneive_lcell_comb \driver|H_SYNC_NEG~0 (
// Equation(s):
// \driver|H_SYNC_NEG~0_combout  = ((\driver|pixel_count [4] & (\driver|pixel_count [5] & \driver|pixel_count [6])) # (!\driver|pixel_count [4] & (!\driver|pixel_count [5] & !\driver|pixel_count [6]))) # (!\driver|pixel_count [7])

	.dataa(\driver|pixel_count [4]),
	.datab(\driver|pixel_count [5]),
	.datac(\driver|pixel_count [7]),
	.datad(\driver|pixel_count [6]),
	.cin(gnd),
	.combout(\driver|H_SYNC_NEG~0_combout ),
	.cout());
// synopsys translate_off
defparam \driver|H_SYNC_NEG~0 .lut_mask = 16'h8F1F;
defparam \driver|H_SYNC_NEG~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y13_N2
cycloneive_lcell_comb \driver|H_SYNC_NEG~1 (
// Equation(s):
// \driver|H_SYNC_NEG~1_combout  = (\driver|pixel_count [8]) # ((\driver|H_SYNC_NEG~0_combout ) # (!\driver|pixel_count [9]))

	.dataa(\driver|pixel_count [8]),
	.datab(\driver|H_SYNC_NEG~0_combout ),
	.datac(\driver|pixel_count [9]),
	.datad(gnd),
	.cin(gnd),
	.combout(\driver|H_SYNC_NEG~1_combout ),
	.cout());
// synopsys translate_off
defparam \driver|H_SYNC_NEG~1 .lut_mask = 16'hEFEF;
defparam \driver|H_SYNC_NEG~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N16
cycloneive_lcell_comb \Mult1|mult_core|romout[1][9]~0 (
// Equation(s):
// \Mult1|mult_core|romout[1][9]~0_combout  = (\driver|line_count [6] & ((\driver|line_count [7] & (\driver|line_count [4] & \driver|line_count [5])) # (!\driver|line_count [7] & ((!\driver|line_count [5]))))) # (!\driver|line_count [6] & 
// ((\driver|line_count [7] & ((\driver|line_count [4]) # (\driver|line_count [5]))) # (!\driver|line_count [7] & (\driver|line_count [4] & \driver|line_count [5]))))

	.dataa(\driver|line_count [6]),
	.datab(\driver|line_count [7]),
	.datac(\driver|line_count [4]),
	.datad(\driver|line_count [5]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[1][9]~0_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[1][9]~0 .lut_mask = 16'hD462;
defparam \Mult1|mult_core|romout[1][9]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N0
cycloneive_lcell_comb \Mult1|mult_core|romout[1][8]~1 (
// Equation(s):
// \Mult1|mult_core|romout[1][8]~1_combout  = (\driver|line_count [6] & ((\driver|line_count [7] & (!\driver|line_count [4] & \driver|line_count [5])) # (!\driver|line_count [7] & (\driver|line_count [4] & !\driver|line_count [5])))) # (!\driver|line_count 
// [6] & ((\driver|line_count [7] & (\driver|line_count [4] $ (!\driver|line_count [5]))) # (!\driver|line_count [7] & (!\driver|line_count [4] & \driver|line_count [5]))))

	.dataa(\driver|line_count [6]),
	.datab(\driver|line_count [7]),
	.datac(\driver|line_count [4]),
	.datad(\driver|line_count [5]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[1][8]~1_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[1][8]~1 .lut_mask = 16'h4924;
defparam \Mult1|mult_core|romout[1][8]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N26
cycloneive_lcell_comb \Mult1|mult_core|romout[1][7]~2 (
// Equation(s):
// \Mult1|mult_core|romout[1][7]~2_combout  = \driver|line_count [7] $ (((\driver|line_count [6] & (\driver|line_count [4] $ (!\driver|line_count [5]))) # (!\driver|line_count [6] & (\driver|line_count [4] & !\driver|line_count [5]))))

	.dataa(\driver|line_count [6]),
	.datab(\driver|line_count [7]),
	.datac(\driver|line_count [4]),
	.datad(\driver|line_count [5]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[1][7]~2_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[1][7]~2 .lut_mask = 16'h6C96;
defparam \Mult1|mult_core|romout[1][7]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N0
cycloneive_lcell_comb \Mult1|mult_core|_~2 (
// Equation(s):
// \Mult1|mult_core|_~2_combout  = (\driver|line_count [3] & \driver|line_count [2])

	.dataa(gnd),
	.datab(\driver|line_count [3]),
	.datac(gnd),
	.datad(\driver|line_count [2]),
	.cin(gnd),
	.combout(\Mult1|mult_core|_~2_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|_~2 .lut_mask = 16'hCC00;
defparam \Mult1|mult_core|_~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N2
cycloneive_lcell_comb \Mult1|mult_core|romout[0][10]~4 (
// Equation(s):
// \Mult1|mult_core|romout[0][10]~4_combout  = (\driver|line_count [3] & ((!\driver|line_count [2]))) # (!\driver|line_count [3] & (\driver|line_count [1] & \driver|line_count [2]))

	.dataa(gnd),
	.datab(\driver|line_count [3]),
	.datac(\driver|line_count [1]),
	.datad(\driver|line_count [2]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[0][10]~4_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[0][10]~4 .lut_mask = 16'h30CC;
defparam \Mult1|mult_core|romout[0][10]~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N28
cycloneive_lcell_comb \Mult1|mult_core|romout[1][6]~3 (
// Equation(s):
// \Mult1|mult_core|romout[1][6]~3_combout  = \driver|line_count [6] $ (((\driver|line_count [5] & !\driver|line_count [4])))

	.dataa(\driver|line_count [6]),
	.datab(\driver|line_count [5]),
	.datac(\driver|line_count [4]),
	.datad(gnd),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[1][6]~3_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[1][6]~3 .lut_mask = 16'hA6A6;
defparam \Mult1|mult_core|romout[1][6]~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N22
cycloneive_lcell_comb \Mult1|mult_core|romout[1][5]~5 (
// Equation(s):
// \Mult1|mult_core|romout[1][5]~5_combout  = \driver|line_count [4] $ (\driver|line_count [5])

	.dataa(gnd),
	.datab(gnd),
	.datac(\driver|line_count [4]),
	.datad(\driver|line_count [5]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[1][5]~5_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[1][5]~5 .lut_mask = 16'h0FF0;
defparam \Mult1|mult_core|romout[1][5]~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N4
cycloneive_lcell_comb \Mult1|mult_core|romout[0][9]~6 (
// Equation(s):
// \Mult1|mult_core|romout[0][9]~6_combout  = (\driver|line_count [3] & ((\driver|line_count [0] & ((\driver|line_count [1]) # (!\driver|line_count [2]))) # (!\driver|line_count [0] & (\driver|line_count [1] & !\driver|line_count [2])))) # 
// (!\driver|line_count [3] & ((\driver|line_count [1] & (\driver|line_count [0] & !\driver|line_count [2])) # (!\driver|line_count [1] & ((\driver|line_count [2])))))

	.dataa(\driver|line_count [0]),
	.datab(\driver|line_count [3]),
	.datac(\driver|line_count [1]),
	.datad(\driver|line_count [2]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[0][9]~6_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[0][9]~6 .lut_mask = 16'h83E8;
defparam \Mult1|mult_core|romout[0][9]~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N6
cycloneive_lcell_comb \Mult1|mult_core|romout[0][8]~7 (
// Equation(s):
// \Mult1|mult_core|romout[0][8]~7_combout  = (\driver|line_count [0] & ((\driver|line_count [3] & (\driver|line_count [1] & !\driver|line_count [2])) # (!\driver|line_count [3] & (!\driver|line_count [1] & \driver|line_count [2])))) # (!\driver|line_count 
// [0] & ((\driver|line_count [3] & (\driver|line_count [1] $ (!\driver|line_count [2]))) # (!\driver|line_count [3] & (\driver|line_count [1] & !\driver|line_count [2]))))

	.dataa(\driver|line_count [0]),
	.datab(\driver|line_count [3]),
	.datac(\driver|line_count [1]),
	.datad(\driver|line_count [2]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[0][8]~7_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[0][8]~7 .lut_mask = 16'h4294;
defparam \Mult1|mult_core|romout[0][8]~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N2
cycloneive_lcell_comb \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0 (
// Equation(s):
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0_combout  = (\Mult1|mult_core|romout[0][8]~7_combout  & (\driver|line_count [4] $ (VCC))) # (!\Mult1|mult_core|romout[0][8]~7_combout  & (\driver|line_count [4] & VCC))
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1  = CARRY((\Mult1|mult_core|romout[0][8]~7_combout  & \driver|line_count [4]))

	.dataa(\Mult1|mult_core|romout[0][8]~7_combout ),
	.datab(\driver|line_count [4]),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ),
	.cout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1 ));
// synopsys translate_off
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688;
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N4
cycloneive_lcell_comb \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2 (
// Equation(s):
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  = (\Mult1|mult_core|romout[1][5]~5_combout  & ((\Mult1|mult_core|romout[0][9]~6_combout  & (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1  & VCC)) # 
// (!\Mult1|mult_core|romout[0][9]~6_combout  & (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1 )))) # (!\Mult1|mult_core|romout[1][5]~5_combout  & ((\Mult1|mult_core|romout[0][9]~6_combout  & (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1 
// )) # (!\Mult1|mult_core|romout[0][9]~6_combout  & ((\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (GND)))))
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~3  = CARRY((\Mult1|mult_core|romout[1][5]~5_combout  & (!\Mult1|mult_core|romout[0][9]~6_combout  & !\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1 )) # (!\Mult1|mult_core|romout[1][5]~5_combout 
//  & ((!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (!\Mult1|mult_core|romout[0][9]~6_combout ))))

	.dataa(\Mult1|mult_core|romout[1][5]~5_combout ),
	.datab(\Mult1|mult_core|romout[0][9]~6_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~1 ),
	.combout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ),
	.cout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~3 ));
// synopsys translate_off
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617;
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N6
cycloneive_lcell_comb \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4 (
// Equation(s):
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4_combout  = ((\Mult1|mult_core|romout[0][10]~4_combout  $ (\Mult1|mult_core|romout[1][6]~3_combout  $ (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~3 )))) # (GND)
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5  = CARRY((\Mult1|mult_core|romout[0][10]~4_combout  & ((\Mult1|mult_core|romout[1][6]~3_combout ) # (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~3 ))) # 
// (!\Mult1|mult_core|romout[0][10]~4_combout  & (\Mult1|mult_core|romout[1][6]~3_combout  & !\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~3 )))

	.dataa(\Mult1|mult_core|romout[0][10]~4_combout ),
	.datab(\Mult1|mult_core|romout[1][6]~3_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~3 ),
	.combout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ),
	.cout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5 ));
// synopsys translate_off
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4 .lut_mask = 16'h698E;
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N8
cycloneive_lcell_comb \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6 (
// Equation(s):
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  = (\Mult1|mult_core|romout[1][7]~2_combout  & ((\Mult1|mult_core|_~2_combout  & (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5  & VCC)) # (!\Mult1|mult_core|_~2_combout  & 
// (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5 )))) # (!\Mult1|mult_core|romout[1][7]~2_combout  & ((\Mult1|mult_core|_~2_combout  & (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5 )) # (!\Mult1|mult_core|_~2_combout  & 
// ((\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (GND)))))
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~7  = CARRY((\Mult1|mult_core|romout[1][7]~2_combout  & (!\Mult1|mult_core|_~2_combout  & !\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5 )) # (!\Mult1|mult_core|romout[1][7]~2_combout  & 
// ((!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (!\Mult1|mult_core|_~2_combout ))))

	.dataa(\Mult1|mult_core|romout[1][7]~2_combout ),
	.datab(\Mult1|mult_core|_~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~5 ),
	.combout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ),
	.cout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~7 ));
// synopsys translate_off
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617;
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N10
cycloneive_lcell_comb \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8 (
// Equation(s):
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8_combout  = (\Mult1|mult_core|romout[1][8]~1_combout  & (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~7  $ (GND))) # (!\Mult1|mult_core|romout[1][8]~1_combout  & 
// (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~7  & VCC))
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~9  = CARRY((\Mult1|mult_core|romout[1][8]~1_combout  & !\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~7 ))

	.dataa(gnd),
	.datab(\Mult1|mult_core|romout[1][8]~1_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~7 ),
	.combout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ),
	.cout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~9 ));
// synopsys translate_off
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8 .lut_mask = 16'hC30C;
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N12
cycloneive_lcell_comb \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10 (
// Equation(s):
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  = (\Mult1|mult_core|romout[1][9]~0_combout  & (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~9 )) # (!\Mult1|mult_core|romout[1][9]~0_combout  & 
// ((\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (GND)))
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~11  = CARRY((!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (!\Mult1|mult_core|romout[1][9]~0_combout ))

	.dataa(gnd),
	.datab(\Mult1|mult_core|romout[1][9]~0_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~9 ),
	.combout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ),
	.cout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~11 ));
// synopsys translate_off
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h3C3F;
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X30_Y10_N8
cycloneive_lcell_comb \Mult1|mult_core|romout[2][5]~8 (
// Equation(s):
// \Mult1|mult_core|romout[2][5]~8_combout  = \driver|line_count [9] $ (\driver|line_count [8])

	.dataa(gnd),
	.datab(gnd),
	.datac(\driver|line_count [9]),
	.datad(\driver|line_count [8]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[2][5]~8_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[2][5]~8 .lut_mask = 16'h0FF0;
defparam \Mult1|mult_core|romout[2][5]~8 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N0
cycloneive_lcell_comb \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 (
// Equation(s):
// \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout  = (\driver|line_count [8] & (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8_combout  $ (VCC))) # (!\driver|line_count [8] & 
// (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8_combout  & VCC))
// \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1  = CARRY((\driver|line_count [8] & \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ))

	.dataa(\driver|line_count [8]),
	.datab(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ),
	.cout(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ));
// synopsys translate_off
defparam \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688;
defparam \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N2
cycloneive_lcell_comb \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 (
// Equation(s):
// \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  = (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  & ((\Mult1|mult_core|romout[2][5]~8_combout  & 
// (\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1  & VCC)) # (!\Mult1|mult_core|romout[2][5]~8_combout  & (!\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )))) # 
// (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  & ((\Mult1|mult_core|romout[2][5]~8_combout  & (!\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )) # (!\Mult1|mult_core|romout[2][5]~8_combout  & 
// ((\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (GND)))))
// \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  = CARRY((\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  & (!\Mult1|mult_core|romout[2][5]~8_combout  & 
// !\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )) # (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  & ((!\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # 
// (!\Mult1|mult_core|romout[2][5]~8_combout ))))

	.dataa(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ),
	.datab(\Mult1|mult_core|romout[2][5]~8_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ),
	.combout(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
	.cout(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ));
// synopsys translate_off
defparam \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617;
defparam \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N12
cycloneive_lcell_comb \Mult1|mult_core|romout[0][7]~9 (
// Equation(s):
// \Mult1|mult_core|romout[0][7]~9_combout  = \driver|line_count [3] $ (((\driver|line_count [1] & (\driver|line_count [0] & \driver|line_count [2])) # (!\driver|line_count [1] & (\driver|line_count [0] $ (\driver|line_count [2])))))

	.dataa(\driver|line_count [1]),
	.datab(\driver|line_count [3]),
	.datac(\driver|line_count [0]),
	.datad(\driver|line_count [2]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[0][7]~9_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[0][7]~9 .lut_mask = 16'h699C;
defparam \Mult1|mult_core|romout[0][7]~9 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N6
cycloneive_lcell_comb \Mult1|mult_core|romout[0][6]~10 (
// Equation(s):
// \Mult1|mult_core|romout[0][6]~10_combout  = \driver|line_count [2] $ (((\driver|line_count [1] & !\driver|line_count [0])))

	.dataa(\driver|line_count [1]),
	.datab(gnd),
	.datac(\driver|line_count [0]),
	.datad(\driver|line_count [2]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[0][6]~10_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[0][6]~10 .lut_mask = 16'hF50A;
defparam \Mult1|mult_core|romout[0][6]~10 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N0
cycloneive_lcell_comb \Mult1|mult_core|romout[0][5]~11 (
// Equation(s):
// \Mult1|mult_core|romout[0][5]~11_combout  = \driver|line_count [0] $ (\driver|line_count [1])

	.dataa(gnd),
	.datab(gnd),
	.datac(\driver|line_count [0]),
	.datad(\driver|line_count [1]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[0][5]~11_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[0][5]~11 .lut_mask = 16'h0FF0;
defparam \Mult1|mult_core|romout[0][5]~11 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N6
cycloneive_lcell_comb \Add3~0 (
// Equation(s):
// \Add3~0_combout  = (\driver|pixel_count [4] & (\driver|line_count [0] $ (VCC))) # (!\driver|pixel_count [4] & (\driver|line_count [0] & VCC))
// \Add3~1  = CARRY((\driver|pixel_count [4] & \driver|line_count [0]))

	.dataa(\driver|pixel_count [4]),
	.datab(\driver|line_count [0]),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\Add3~0_combout ),
	.cout(\Add3~1 ));
// synopsys translate_off
defparam \Add3~0 .lut_mask = 16'h6688;
defparam \Add3~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N8
cycloneive_lcell_comb \Add3~2 (
// Equation(s):
// \Add3~2_combout  = (\Mult1|mult_core|romout[0][5]~11_combout  & ((\driver|pixel_count [5] & (\Add3~1  & VCC)) # (!\driver|pixel_count [5] & (!\Add3~1 )))) # (!\Mult1|mult_core|romout[0][5]~11_combout  & ((\driver|pixel_count [5] & (!\Add3~1 )) # 
// (!\driver|pixel_count [5] & ((\Add3~1 ) # (GND)))))
// \Add3~3  = CARRY((\Mult1|mult_core|romout[0][5]~11_combout  & (!\driver|pixel_count [5] & !\Add3~1 )) # (!\Mult1|mult_core|romout[0][5]~11_combout  & ((!\Add3~1 ) # (!\driver|pixel_count [5]))))

	.dataa(\Mult1|mult_core|romout[0][5]~11_combout ),
	.datab(\driver|pixel_count [5]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~1 ),
	.combout(\Add3~2_combout ),
	.cout(\Add3~3 ));
// synopsys translate_off
defparam \Add3~2 .lut_mask = 16'h9617;
defparam \Add3~2 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N10
cycloneive_lcell_comb \Add3~4 (
// Equation(s):
// \Add3~4_combout  = ((\driver|pixel_count [6] $ (\Mult1|mult_core|romout[0][6]~10_combout  $ (!\Add3~3 )))) # (GND)
// \Add3~5  = CARRY((\driver|pixel_count [6] & ((\Mult1|mult_core|romout[0][6]~10_combout ) # (!\Add3~3 ))) # (!\driver|pixel_count [6] & (\Mult1|mult_core|romout[0][6]~10_combout  & !\Add3~3 )))

	.dataa(\driver|pixel_count [6]),
	.datab(\Mult1|mult_core|romout[0][6]~10_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~3 ),
	.combout(\Add3~4_combout ),
	.cout(\Add3~5 ));
// synopsys translate_off
defparam \Add3~4 .lut_mask = 16'h698E;
defparam \Add3~4 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N12
cycloneive_lcell_comb \Add3~6 (
// Equation(s):
// \Add3~6_combout  = (\Mult1|mult_core|romout[0][7]~9_combout  & ((\driver|pixel_count [7] & (\Add3~5  & VCC)) # (!\driver|pixel_count [7] & (!\Add3~5 )))) # (!\Mult1|mult_core|romout[0][7]~9_combout  & ((\driver|pixel_count [7] & (!\Add3~5 )) # 
// (!\driver|pixel_count [7] & ((\Add3~5 ) # (GND)))))
// \Add3~7  = CARRY((\Mult1|mult_core|romout[0][7]~9_combout  & (!\driver|pixel_count [7] & !\Add3~5 )) # (!\Mult1|mult_core|romout[0][7]~9_combout  & ((!\Add3~5 ) # (!\driver|pixel_count [7]))))

	.dataa(\Mult1|mult_core|romout[0][7]~9_combout ),
	.datab(\driver|pixel_count [7]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~5 ),
	.combout(\Add3~6_combout ),
	.cout(\Add3~7 ));
// synopsys translate_off
defparam \Add3~6 .lut_mask = 16'h9617;
defparam \Add3~6 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N14
cycloneive_lcell_comb \Add3~8 (
// Equation(s):
// \Add3~8_combout  = ((\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0_combout  $ (\driver|pixel_count [8] $ (!\Add3~7 )))) # (GND)
// \Add3~9  = CARRY((\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0_combout  & ((\driver|pixel_count [8]) # (!\Add3~7 ))) # (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0_combout  & (\driver|pixel_count [8] & !\Add3~7 )))

	.dataa(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ),
	.datab(\driver|pixel_count [8]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~7 ),
	.combout(\Add3~8_combout ),
	.cout(\Add3~9 ));
// synopsys translate_off
defparam \Add3~8 .lut_mask = 16'h698E;
defparam \Add3~8 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N16
cycloneive_lcell_comb \Add3~10 (
// Equation(s):
// \Add3~10_combout  = (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  & ((\driver|pixel_count [9] & (\Add3~9  & VCC)) # (!\driver|pixel_count [9] & (!\Add3~9 )))) # (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  & 
// ((\driver|pixel_count [9] & (!\Add3~9 )) # (!\driver|pixel_count [9] & ((\Add3~9 ) # (GND)))))
// \Add3~11  = CARRY((\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  & (!\driver|pixel_count [9] & !\Add3~9 )) # (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  & ((!\Add3~9 ) # (!\driver|pixel_count [9]))))

	.dataa(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ),
	.datab(\driver|pixel_count [9]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~9 ),
	.combout(\Add3~10_combout ),
	.cout(\Add3~11 ));
// synopsys translate_off
defparam \Add3~10 .lut_mask = 16'h9617;
defparam \Add3~10 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N18
cycloneive_lcell_comb \Add3~12 (
// Equation(s):
// \Add3~12_combout  = (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4_combout  & (\Add3~11  $ (GND))) # (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4_combout  & (!\Add3~11  & VCC))
// \Add3~13  = CARRY((\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4_combout  & !\Add3~11 ))

	.dataa(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~11 ),
	.combout(\Add3~12_combout ),
	.cout(\Add3~13 ));
// synopsys translate_off
defparam \Add3~12 .lut_mask = 16'hA50A;
defparam \Add3~12 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N20
cycloneive_lcell_comb \Add3~14 (
// Equation(s):
// \Add3~14_combout  = (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  & (!\Add3~13 )) # (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  & ((\Add3~13 ) # (GND)))
// \Add3~15  = CARRY((!\Add3~13 ) # (!\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ))

	.dataa(gnd),
	.datab(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~13 ),
	.combout(\Add3~14_combout ),
	.cout(\Add3~15 ));
// synopsys translate_off
defparam \Add3~14 .lut_mask = 16'h3C3F;
defparam \Add3~14 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N22
cycloneive_lcell_comb \Add3~16 (
// Equation(s):
// \Add3~16_combout  = (\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout  & (\Add3~15  $ (GND))) # (!\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout  & (!\Add3~15  & VCC))
// \Add3~17  = CARRY((\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout  & !\Add3~15 ))

	.dataa(gnd),
	.datab(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~15 ),
	.combout(\Add3~16_combout ),
	.cout(\Add3~17 ));
// synopsys translate_off
defparam \Add3~16 .lut_mask = 16'hC30C;
defparam \Add3~16 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N24
cycloneive_lcell_comb \Add3~18 (
// Equation(s):
// \Add3~18_combout  = (\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\Add3~17 )) # (!\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\Add3~17 ) # (GND)))
// \Add3~19  = CARRY((!\Add3~17 ) # (!\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ))

	.dataa(gnd),
	.datab(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add3~17 ),
	.combout(\Add3~18_combout ),
	.cout(\Add3~19 ));
// synopsys translate_off
defparam \Add3~18 .lut_mask = 16'h3C3F;
defparam \Add3~18 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X28_Y10_N25
dffeas \mem|mem_rtl_0|auto_generated|address_reg_b[0] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\Add3~18_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.prn(vcc));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|address_reg_b[0] .is_wysiwyg = "true";
defparam \mem|mem_rtl_0|auto_generated|address_reg_b[0] .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X53_Y16_N8
cycloneive_io_ibuf \GPIO_1_D[32]~input (
	.i(GPIO_1_D[32]),
	.ibar(gnd),
	.o(\GPIO_1_D[32]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[32]~input .bus_hold = "false";
defparam \GPIO_1_D[32]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X53_Y15_N8
cycloneive_io_ibuf \GPIO_1_D[33]~input (
	.i(GPIO_1_D[33]),
	.ibar(gnd),
	.o(\GPIO_1_D[33]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[33]~input .bus_hold = "false";
defparam \GPIO_1_D[33]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X34_Y15_N28
cycloneive_lcell_comb \pixel_data_RGB332[0]~0 (
// Equation(s):
// \pixel_data_RGB332[0]~0_combout  = (!\is_lsb~q  & \GPIO_1_D[33]~input_o )

	.dataa(gnd),
	.datab(gnd),
	.datac(\is_lsb~q ),
	.datad(\GPIO_1_D[33]~input_o ),
	.cin(gnd),
	.combout(\pixel_data_RGB332[0]~0_combout ),
	.cout());
// synopsys translate_off
defparam \pixel_data_RGB332[0]~0 .lut_mask = 16'h0F00;
defparam \pixel_data_RGB332[0]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y15_N22
cycloneive_lcell_comb \is_lsb~feeder (
// Equation(s):
// \is_lsb~feeder_combout  = \pixel_data_RGB332[0]~0_combout 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\pixel_data_RGB332[0]~0_combout ),
	.cin(gnd),
	.combout(\is_lsb~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \is_lsb~feeder .lut_mask = 16'hFF00;
defparam \is_lsb~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X34_Y15_N23
dffeas is_lsb(
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\is_lsb~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\is_lsb~q ),
	.prn(vcc));
// synopsys translate_off
defparam is_lsb.is_wysiwyg = "true";
defparam is_lsb.power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N2
cycloneive_lcell_comb \X_ADDR[0]~15 (
// Equation(s):
// \X_ADDR[0]~15_combout  = (X_ADDR[0] & (\is_lsb~q  $ (VCC))) # (!X_ADDR[0] & (\is_lsb~q  & VCC))
// \X_ADDR[0]~16  = CARRY((X_ADDR[0] & \is_lsb~q ))

	.dataa(X_ADDR[0]),
	.datab(\is_lsb~q ),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\X_ADDR[0]~15_combout ),
	.cout(\X_ADDR[0]~16 ));
// synopsys translate_off
defparam \X_ADDR[0]~15 .lut_mask = 16'h6688;
defparam \X_ADDR[0]~15 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y15_N18
cycloneive_lcell_comb \last_href~feeder (
// Equation(s):
// \last_href~feeder_combout  = \GPIO_1_D[33]~input_o 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\GPIO_1_D[33]~input_o ),
	.cin(gnd),
	.combout(\last_href~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \last_href~feeder .lut_mask = 16'hFF00;
defparam \last_href~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X34_Y15_N19
dffeas last_href(
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\last_href~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\last_href~q ),
	.prn(vcc));
// synopsys translate_off
defparam last_href.is_wysiwyg = "true";
defparam last_href.power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X53_Y14_N8
cycloneive_io_ibuf \GPIO_1_D[30]~input (
	.i(GPIO_1_D[30]),
	.ibar(gnd),
	.o(\GPIO_1_D[30]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[30]~input .bus_hold = "false";
defparam \GPIO_1_D[30]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X34_Y15_N0
cycloneive_lcell_comb \X_ADDR[13]~43 (
// Equation(s):
// \X_ADDR[13]~43_combout  = (\last_href~q ) # ((\GPIO_1_D[30]~input_o ) # (\GPIO_1_D[33]~input_o ))

	.dataa(gnd),
	.datab(\last_href~q ),
	.datac(\GPIO_1_D[30]~input_o ),
	.datad(\GPIO_1_D[33]~input_o ),
	.cin(gnd),
	.combout(\X_ADDR[13]~43_combout ),
	.cout());
// synopsys translate_off
defparam \X_ADDR[13]~43 .lut_mask = 16'hFFFC;
defparam \X_ADDR[13]~43 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X30_Y18_N3
dffeas \X_ADDR[0] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[0]~15_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[0]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[0] .is_wysiwyg = "true";
defparam \X_ADDR[0] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N4
cycloneive_lcell_comb \X_ADDR[1]~17 (
// Equation(s):
// \X_ADDR[1]~17_combout  = (X_ADDR[1] & (!\X_ADDR[0]~16 )) # (!X_ADDR[1] & ((\X_ADDR[0]~16 ) # (GND)))
// \X_ADDR[1]~18  = CARRY((!\X_ADDR[0]~16 ) # (!X_ADDR[1]))

	.dataa(gnd),
	.datab(X_ADDR[1]),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[0]~16 ),
	.combout(\X_ADDR[1]~17_combout ),
	.cout(\X_ADDR[1]~18 ));
// synopsys translate_off
defparam \X_ADDR[1]~17 .lut_mask = 16'h3C3F;
defparam \X_ADDR[1]~17 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N5
dffeas \X_ADDR[1] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[1]~17_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[1]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[1] .is_wysiwyg = "true";
defparam \X_ADDR[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N6
cycloneive_lcell_comb \X_ADDR[2]~19 (
// Equation(s):
// \X_ADDR[2]~19_combout  = (X_ADDR[2] & (\X_ADDR[1]~18  $ (GND))) # (!X_ADDR[2] & (!\X_ADDR[1]~18  & VCC))
// \X_ADDR[2]~20  = CARRY((X_ADDR[2] & !\X_ADDR[1]~18 ))

	.dataa(X_ADDR[2]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[1]~18 ),
	.combout(\X_ADDR[2]~19_combout ),
	.cout(\X_ADDR[2]~20 ));
// synopsys translate_off
defparam \X_ADDR[2]~19 .lut_mask = 16'hA50A;
defparam \X_ADDR[2]~19 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N7
dffeas \X_ADDR[2] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[2]~19_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[2]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[2] .is_wysiwyg = "true";
defparam \X_ADDR[2] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N8
cycloneive_lcell_comb \X_ADDR[3]~21 (
// Equation(s):
// \X_ADDR[3]~21_combout  = (X_ADDR[3] & (!\X_ADDR[2]~20 )) # (!X_ADDR[3] & ((\X_ADDR[2]~20 ) # (GND)))
// \X_ADDR[3]~22  = CARRY((!\X_ADDR[2]~20 ) # (!X_ADDR[3]))

	.dataa(gnd),
	.datab(X_ADDR[3]),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[2]~20 ),
	.combout(\X_ADDR[3]~21_combout ),
	.cout(\X_ADDR[3]~22 ));
// synopsys translate_off
defparam \X_ADDR[3]~21 .lut_mask = 16'h3C3F;
defparam \X_ADDR[3]~21 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N9
dffeas \X_ADDR[3] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[3]~21_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[3]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[3] .is_wysiwyg = "true";
defparam \X_ADDR[3] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N10
cycloneive_lcell_comb \X_ADDR[4]~23 (
// Equation(s):
// \X_ADDR[4]~23_combout  = (X_ADDR[4] & (\X_ADDR[3]~22  $ (GND))) # (!X_ADDR[4] & (!\X_ADDR[3]~22  & VCC))
// \X_ADDR[4]~24  = CARRY((X_ADDR[4] & !\X_ADDR[3]~22 ))

	.dataa(X_ADDR[4]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[3]~22 ),
	.combout(\X_ADDR[4]~23_combout ),
	.cout(\X_ADDR[4]~24 ));
// synopsys translate_off
defparam \X_ADDR[4]~23 .lut_mask = 16'hA50A;
defparam \X_ADDR[4]~23 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N11
dffeas \X_ADDR[4] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[4]~23_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[4]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[4] .is_wysiwyg = "true";
defparam \X_ADDR[4] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N12
cycloneive_lcell_comb \X_ADDR[5]~25 (
// Equation(s):
// \X_ADDR[5]~25_combout  = (X_ADDR[5] & (!\X_ADDR[4]~24 )) # (!X_ADDR[5] & ((\X_ADDR[4]~24 ) # (GND)))
// \X_ADDR[5]~26  = CARRY((!\X_ADDR[4]~24 ) # (!X_ADDR[5]))

	.dataa(X_ADDR[5]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[4]~24 ),
	.combout(\X_ADDR[5]~25_combout ),
	.cout(\X_ADDR[5]~26 ));
// synopsys translate_off
defparam \X_ADDR[5]~25 .lut_mask = 16'h5A5F;
defparam \X_ADDR[5]~25 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N13
dffeas \X_ADDR[5] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[5]~25_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[5]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[5] .is_wysiwyg = "true";
defparam \X_ADDR[5] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N14
cycloneive_lcell_comb \X_ADDR[6]~27 (
// Equation(s):
// \X_ADDR[6]~27_combout  = (X_ADDR[6] & (\X_ADDR[5]~26  $ (GND))) # (!X_ADDR[6] & (!\X_ADDR[5]~26  & VCC))
// \X_ADDR[6]~28  = CARRY((X_ADDR[6] & !\X_ADDR[5]~26 ))

	.dataa(gnd),
	.datab(X_ADDR[6]),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[5]~26 ),
	.combout(\X_ADDR[6]~27_combout ),
	.cout(\X_ADDR[6]~28 ));
// synopsys translate_off
defparam \X_ADDR[6]~27 .lut_mask = 16'hC30C;
defparam \X_ADDR[6]~27 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N15
dffeas \X_ADDR[6] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[6]~27_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[6]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[6] .is_wysiwyg = "true";
defparam \X_ADDR[6] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N16
cycloneive_lcell_comb \X_ADDR[7]~29 (
// Equation(s):
// \X_ADDR[7]~29_combout  = (X_ADDR[7] & (!\X_ADDR[6]~28 )) # (!X_ADDR[7] & ((\X_ADDR[6]~28 ) # (GND)))
// \X_ADDR[7]~30  = CARRY((!\X_ADDR[6]~28 ) # (!X_ADDR[7]))

	.dataa(gnd),
	.datab(X_ADDR[7]),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[6]~28 ),
	.combout(\X_ADDR[7]~29_combout ),
	.cout(\X_ADDR[7]~30 ));
// synopsys translate_off
defparam \X_ADDR[7]~29 .lut_mask = 16'h3C3F;
defparam \X_ADDR[7]~29 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N17
dffeas \X_ADDR[7] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[7]~29_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[7]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[7] .is_wysiwyg = "true";
defparam \X_ADDR[7] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N18
cycloneive_lcell_comb \X_ADDR[8]~31 (
// Equation(s):
// \X_ADDR[8]~31_combout  = (X_ADDR[8] & (\X_ADDR[7]~30  $ (GND))) # (!X_ADDR[8] & (!\X_ADDR[7]~30  & VCC))
// \X_ADDR[8]~32  = CARRY((X_ADDR[8] & !\X_ADDR[7]~30 ))

	.dataa(gnd),
	.datab(X_ADDR[8]),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[7]~30 ),
	.combout(\X_ADDR[8]~31_combout ),
	.cout(\X_ADDR[8]~32 ));
// synopsys translate_off
defparam \X_ADDR[8]~31 .lut_mask = 16'hC30C;
defparam \X_ADDR[8]~31 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N19
dffeas \X_ADDR[8] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[8]~31_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[8]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[8] .is_wysiwyg = "true";
defparam \X_ADDR[8] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N20
cycloneive_lcell_comb \X_ADDR[9]~33 (
// Equation(s):
// \X_ADDR[9]~33_combout  = (X_ADDR[9] & (!\X_ADDR[8]~32 )) # (!X_ADDR[9] & ((\X_ADDR[8]~32 ) # (GND)))
// \X_ADDR[9]~34  = CARRY((!\X_ADDR[8]~32 ) # (!X_ADDR[9]))

	.dataa(gnd),
	.datab(X_ADDR[9]),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[8]~32 ),
	.combout(\X_ADDR[9]~33_combout ),
	.cout(\X_ADDR[9]~34 ));
// synopsys translate_off
defparam \X_ADDR[9]~33 .lut_mask = 16'h3C3F;
defparam \X_ADDR[9]~33 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N21
dffeas \X_ADDR[9] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[9]~33_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[9]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[9] .is_wysiwyg = "true";
defparam \X_ADDR[9] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N22
cycloneive_lcell_comb \X_ADDR[10]~35 (
// Equation(s):
// \X_ADDR[10]~35_combout  = (X_ADDR[10] & (\X_ADDR[9]~34  $ (GND))) # (!X_ADDR[10] & (!\X_ADDR[9]~34  & VCC))
// \X_ADDR[10]~36  = CARRY((X_ADDR[10] & !\X_ADDR[9]~34 ))

	.dataa(X_ADDR[10]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[9]~34 ),
	.combout(\X_ADDR[10]~35_combout ),
	.cout(\X_ADDR[10]~36 ));
// synopsys translate_off
defparam \X_ADDR[10]~35 .lut_mask = 16'hA50A;
defparam \X_ADDR[10]~35 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N23
dffeas \X_ADDR[10] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[10]~35_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[10]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[10] .is_wysiwyg = "true";
defparam \X_ADDR[10] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N24
cycloneive_lcell_comb \X_ADDR[11]~37 (
// Equation(s):
// \X_ADDR[11]~37_combout  = (X_ADDR[11] & (!\X_ADDR[10]~36 )) # (!X_ADDR[11] & ((\X_ADDR[10]~36 ) # (GND)))
// \X_ADDR[11]~38  = CARRY((!\X_ADDR[10]~36 ) # (!X_ADDR[11]))

	.dataa(gnd),
	.datab(X_ADDR[11]),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[10]~36 ),
	.combout(\X_ADDR[11]~37_combout ),
	.cout(\X_ADDR[11]~38 ));
// synopsys translate_off
defparam \X_ADDR[11]~37 .lut_mask = 16'h3C3F;
defparam \X_ADDR[11]~37 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N25
dffeas \X_ADDR[11] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[11]~37_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[11]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[11] .is_wysiwyg = "true";
defparam \X_ADDR[11] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N26
cycloneive_lcell_comb \X_ADDR[12]~39 (
// Equation(s):
// \X_ADDR[12]~39_combout  = (X_ADDR[12] & (\X_ADDR[11]~38  $ (GND))) # (!X_ADDR[12] & (!\X_ADDR[11]~38  & VCC))
// \X_ADDR[12]~40  = CARRY((X_ADDR[12] & !\X_ADDR[11]~38 ))

	.dataa(X_ADDR[12]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[11]~38 ),
	.combout(\X_ADDR[12]~39_combout ),
	.cout(\X_ADDR[12]~40 ));
// synopsys translate_off
defparam \X_ADDR[12]~39 .lut_mask = 16'hA50A;
defparam \X_ADDR[12]~39 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N27
dffeas \X_ADDR[12] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[12]~39_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[12]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[12] .is_wysiwyg = "true";
defparam \X_ADDR[12] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N28
cycloneive_lcell_comb \X_ADDR[13]~41 (
// Equation(s):
// \X_ADDR[13]~41_combout  = (X_ADDR[13] & (!\X_ADDR[12]~40 )) # (!X_ADDR[13] & ((\X_ADDR[12]~40 ) # (GND)))
// \X_ADDR[13]~42  = CARRY((!\X_ADDR[12]~40 ) # (!X_ADDR[13]))

	.dataa(gnd),
	.datab(X_ADDR[13]),
	.datac(gnd),
	.datad(vcc),
	.cin(\X_ADDR[12]~40 ),
	.combout(\X_ADDR[13]~41_combout ),
	.cout(\X_ADDR[13]~42 ));
// synopsys translate_off
defparam \X_ADDR[13]~41 .lut_mask = 16'h3C3F;
defparam \X_ADDR[13]~41 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N29
dffeas \X_ADDR[13] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[13]~41_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[13]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[13] .is_wysiwyg = "true";
defparam \X_ADDR[13] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N2
cycloneive_lcell_comb \Y_ADDR[0]~15 (
// Equation(s):
// \Y_ADDR[0]~15_combout  = (\last_href~q  & (Y_ADDR[0] $ (VCC))) # (!\last_href~q  & (Y_ADDR[0] & VCC))
// \Y_ADDR[0]~16  = CARRY((\last_href~q  & Y_ADDR[0]))

	.dataa(\last_href~q ),
	.datab(Y_ADDR[0]),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\Y_ADDR[0]~15_combout ),
	.cout(\Y_ADDR[0]~16 ));
// synopsys translate_off
defparam \Y_ADDR[0]~15 .lut_mask = 16'h6688;
defparam \Y_ADDR[0]~15 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y15_N4
cycloneive_lcell_comb \always0~0 (
// Equation(s):
// \always0~0_combout  = (!\last_href~q  & (\GPIO_1_D[30]~input_o  & !\GPIO_1_D[33]~input_o ))

	.dataa(gnd),
	.datab(\last_href~q ),
	.datac(\GPIO_1_D[30]~input_o ),
	.datad(\GPIO_1_D[33]~input_o ),
	.cin(gnd),
	.combout(\always0~0_combout ),
	.cout());
// synopsys translate_off
defparam \always0~0 .lut_mask = 16'h0030;
defparam \always0~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X34_Y18_N3
dffeas \Y_ADDR[0] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[0]~15_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[0]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[0] .is_wysiwyg = "true";
defparam \Y_ADDR[0] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N4
cycloneive_lcell_comb \Y_ADDR[1]~17 (
// Equation(s):
// \Y_ADDR[1]~17_combout  = (Y_ADDR[1] & (!\Y_ADDR[0]~16 )) # (!Y_ADDR[1] & ((\Y_ADDR[0]~16 ) # (GND)))
// \Y_ADDR[1]~18  = CARRY((!\Y_ADDR[0]~16 ) # (!Y_ADDR[1]))

	.dataa(gnd),
	.datab(Y_ADDR[1]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[0]~16 ),
	.combout(\Y_ADDR[1]~17_combout ),
	.cout(\Y_ADDR[1]~18 ));
// synopsys translate_off
defparam \Y_ADDR[1]~17 .lut_mask = 16'h3C3F;
defparam \Y_ADDR[1]~17 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N5
dffeas \Y_ADDR[1] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[1]~17_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[1]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[1] .is_wysiwyg = "true";
defparam \Y_ADDR[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N6
cycloneive_lcell_comb \Y_ADDR[2]~19 (
// Equation(s):
// \Y_ADDR[2]~19_combout  = (Y_ADDR[2] & (\Y_ADDR[1]~18  $ (GND))) # (!Y_ADDR[2] & (!\Y_ADDR[1]~18  & VCC))
// \Y_ADDR[2]~20  = CARRY((Y_ADDR[2] & !\Y_ADDR[1]~18 ))

	.dataa(Y_ADDR[2]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[1]~18 ),
	.combout(\Y_ADDR[2]~19_combout ),
	.cout(\Y_ADDR[2]~20 ));
// synopsys translate_off
defparam \Y_ADDR[2]~19 .lut_mask = 16'hA50A;
defparam \Y_ADDR[2]~19 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N7
dffeas \Y_ADDR[2] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[2]~19_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[2]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[2] .is_wysiwyg = "true";
defparam \Y_ADDR[2] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N8
cycloneive_lcell_comb \Y_ADDR[3]~21 (
// Equation(s):
// \Y_ADDR[3]~21_combout  = (Y_ADDR[3] & (!\Y_ADDR[2]~20 )) # (!Y_ADDR[3] & ((\Y_ADDR[2]~20 ) # (GND)))
// \Y_ADDR[3]~22  = CARRY((!\Y_ADDR[2]~20 ) # (!Y_ADDR[3]))

	.dataa(gnd),
	.datab(Y_ADDR[3]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[2]~20 ),
	.combout(\Y_ADDR[3]~21_combout ),
	.cout(\Y_ADDR[3]~22 ));
// synopsys translate_off
defparam \Y_ADDR[3]~21 .lut_mask = 16'h3C3F;
defparam \Y_ADDR[3]~21 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N9
dffeas \Y_ADDR[3] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[3]~21_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[3]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[3] .is_wysiwyg = "true";
defparam \Y_ADDR[3] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N10
cycloneive_lcell_comb \Y_ADDR[4]~23 (
// Equation(s):
// \Y_ADDR[4]~23_combout  = (Y_ADDR[4] & (\Y_ADDR[3]~22  $ (GND))) # (!Y_ADDR[4] & (!\Y_ADDR[3]~22  & VCC))
// \Y_ADDR[4]~24  = CARRY((Y_ADDR[4] & !\Y_ADDR[3]~22 ))

	.dataa(Y_ADDR[4]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[3]~22 ),
	.combout(\Y_ADDR[4]~23_combout ),
	.cout(\Y_ADDR[4]~24 ));
// synopsys translate_off
defparam \Y_ADDR[4]~23 .lut_mask = 16'hA50A;
defparam \Y_ADDR[4]~23 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N11
dffeas \Y_ADDR[4] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[4]~23_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[4]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[4] .is_wysiwyg = "true";
defparam \Y_ADDR[4] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N12
cycloneive_lcell_comb \Y_ADDR[5]~25 (
// Equation(s):
// \Y_ADDR[5]~25_combout  = (Y_ADDR[5] & (!\Y_ADDR[4]~24 )) # (!Y_ADDR[5] & ((\Y_ADDR[4]~24 ) # (GND)))
// \Y_ADDR[5]~26  = CARRY((!\Y_ADDR[4]~24 ) # (!Y_ADDR[5]))

	.dataa(Y_ADDR[5]),
	.datab(gnd),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[4]~24 ),
	.combout(\Y_ADDR[5]~25_combout ),
	.cout(\Y_ADDR[5]~26 ));
// synopsys translate_off
defparam \Y_ADDR[5]~25 .lut_mask = 16'h5A5F;
defparam \Y_ADDR[5]~25 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N13
dffeas \Y_ADDR[5] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[5]~25_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[5]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[5] .is_wysiwyg = "true";
defparam \Y_ADDR[5] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N14
cycloneive_lcell_comb \Y_ADDR[6]~27 (
// Equation(s):
// \Y_ADDR[6]~27_combout  = (Y_ADDR[6] & (\Y_ADDR[5]~26  $ (GND))) # (!Y_ADDR[6] & (!\Y_ADDR[5]~26  & VCC))
// \Y_ADDR[6]~28  = CARRY((Y_ADDR[6] & !\Y_ADDR[5]~26 ))

	.dataa(gnd),
	.datab(Y_ADDR[6]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[5]~26 ),
	.combout(\Y_ADDR[6]~27_combout ),
	.cout(\Y_ADDR[6]~28 ));
// synopsys translate_off
defparam \Y_ADDR[6]~27 .lut_mask = 16'hC30C;
defparam \Y_ADDR[6]~27 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N15
dffeas \Y_ADDR[6] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[6]~27_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[6]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[6] .is_wysiwyg = "true";
defparam \Y_ADDR[6] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N16
cycloneive_lcell_comb \Y_ADDR[7]~29 (
// Equation(s):
// \Y_ADDR[7]~29_combout  = (Y_ADDR[7] & (!\Y_ADDR[6]~28 )) # (!Y_ADDR[7] & ((\Y_ADDR[6]~28 ) # (GND)))
// \Y_ADDR[7]~30  = CARRY((!\Y_ADDR[6]~28 ) # (!Y_ADDR[7]))

	.dataa(gnd),
	.datab(Y_ADDR[7]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[6]~28 ),
	.combout(\Y_ADDR[7]~29_combout ),
	.cout(\Y_ADDR[7]~30 ));
// synopsys translate_off
defparam \Y_ADDR[7]~29 .lut_mask = 16'h3C3F;
defparam \Y_ADDR[7]~29 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N17
dffeas \Y_ADDR[7] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[7]~29_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[7]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[7] .is_wysiwyg = "true";
defparam \Y_ADDR[7] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N8
cycloneive_lcell_comb \Mult0|mult_core|romout[1][9]~0 (
// Equation(s):
// \Mult0|mult_core|romout[1][9]~0_combout  = (Y_ADDR[6] & ((Y_ADDR[5] & (Y_ADDR[7] & Y_ADDR[4])) # (!Y_ADDR[5] & (!Y_ADDR[7])))) # (!Y_ADDR[6] & ((Y_ADDR[5] & ((Y_ADDR[7]) # (Y_ADDR[4]))) # (!Y_ADDR[5] & (Y_ADDR[7] & Y_ADDR[4]))))

	.dataa(Y_ADDR[6]),
	.datab(Y_ADDR[5]),
	.datac(Y_ADDR[7]),
	.datad(Y_ADDR[4]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[1][9]~0_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[1][9]~0 .lut_mask = 16'hD642;
defparam \Mult0|mult_core|romout[1][9]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N2
cycloneive_lcell_comb \Mult0|mult_core|romout[1][8]~1 (
// Equation(s):
// \Mult0|mult_core|romout[1][8]~1_combout  = (Y_ADDR[6] & ((Y_ADDR[5] & (Y_ADDR[7] & !Y_ADDR[4])) # (!Y_ADDR[5] & (!Y_ADDR[7] & Y_ADDR[4])))) # (!Y_ADDR[6] & ((Y_ADDR[5] & (Y_ADDR[7] $ (!Y_ADDR[4]))) # (!Y_ADDR[5] & (Y_ADDR[7] & !Y_ADDR[4]))))

	.dataa(Y_ADDR[6]),
	.datab(Y_ADDR[5]),
	.datac(Y_ADDR[7]),
	.datad(Y_ADDR[4]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[1][8]~1_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[1][8]~1 .lut_mask = 16'h4294;
defparam \Mult0|mult_core|romout[1][8]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y17_N0
cycloneive_lcell_comb \Mult0|mult_core|_~0 (
// Equation(s):
// \Mult0|mult_core|_~0_combout  = (Y_ADDR[3] & Y_ADDR[2])

	.dataa(gnd),
	.datab(Y_ADDR[3]),
	.datac(Y_ADDR[2]),
	.datad(gnd),
	.cin(gnd),
	.combout(\Mult0|mult_core|_~0_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|_~0 .lut_mask = 16'hC0C0;
defparam \Mult0|mult_core|_~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N4
cycloneive_lcell_comb \Mult0|mult_core|romout[1][7]~2 (
// Equation(s):
// \Mult0|mult_core|romout[1][7]~2_combout  = Y_ADDR[7] $ (((Y_ADDR[6] & (Y_ADDR[5] $ (!Y_ADDR[4]))) # (!Y_ADDR[6] & (!Y_ADDR[5] & Y_ADDR[4]))))

	.dataa(Y_ADDR[6]),
	.datab(Y_ADDR[5]),
	.datac(Y_ADDR[7]),
	.datad(Y_ADDR[4]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[1][7]~2_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[1][7]~2 .lut_mask = 16'h69D2;
defparam \Mult0|mult_core|romout[1][7]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N6
cycloneive_lcell_comb \Mult0|mult_core|romout[1][6]~3 (
// Equation(s):
// \Mult0|mult_core|romout[1][6]~3_combout  = Y_ADDR[6] $ (((Y_ADDR[5] & !Y_ADDR[4])))

	.dataa(Y_ADDR[6]),
	.datab(gnd),
	.datac(Y_ADDR[5]),
	.datad(Y_ADDR[4]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[1][6]~3_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[1][6]~3 .lut_mask = 16'hAA5A;
defparam \Mult0|mult_core|romout[1][6]~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N24
cycloneive_lcell_comb \Mult0|mult_core|romout[0][10]~4 (
// Equation(s):
// \Mult0|mult_core|romout[0][10]~4_combout  = (Y_ADDR[3] & ((!Y_ADDR[2]))) # (!Y_ADDR[3] & (Y_ADDR[1] & Y_ADDR[2]))

	.dataa(gnd),
	.datab(Y_ADDR[3]),
	.datac(Y_ADDR[1]),
	.datad(Y_ADDR[2]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[0][10]~4_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[0][10]~4 .lut_mask = 16'h30CC;
defparam \Mult0|mult_core|romout[0][10]~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N0
cycloneive_lcell_comb \Mult0|mult_core|romout[0][9]~6 (
// Equation(s):
// \Mult0|mult_core|romout[0][9]~6_combout  = (Y_ADDR[2] & ((Y_ADDR[3] & (Y_ADDR[1] & Y_ADDR[0])) # (!Y_ADDR[3] & (!Y_ADDR[1])))) # (!Y_ADDR[2] & ((Y_ADDR[3] & ((Y_ADDR[1]) # (Y_ADDR[0]))) # (!Y_ADDR[3] & (Y_ADDR[1] & Y_ADDR[0]))))

	.dataa(Y_ADDR[2]),
	.datab(Y_ADDR[3]),
	.datac(Y_ADDR[1]),
	.datad(Y_ADDR[0]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[0][9]~6_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[0][9]~6 .lut_mask = 16'hD642;
defparam \Mult0|mult_core|romout[0][9]~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N0
cycloneive_lcell_comb \Mult0|mult_core|romout[1][5]~5 (
// Equation(s):
// \Mult0|mult_core|romout[1][5]~5_combout  = Y_ADDR[5] $ (Y_ADDR[4])

	.dataa(Y_ADDR[5]),
	.datab(gnd),
	.datac(gnd),
	.datad(Y_ADDR[4]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[1][5]~5_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[1][5]~5 .lut_mask = 16'h55AA;
defparam \Mult0|mult_core|romout[1][5]~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N26
cycloneive_lcell_comb \Mult0|mult_core|romout[0][8]~7 (
// Equation(s):
// \Mult0|mult_core|romout[0][8]~7_combout  = (Y_ADDR[2] & ((Y_ADDR[3] & (Y_ADDR[1] & !Y_ADDR[0])) # (!Y_ADDR[3] & (!Y_ADDR[1] & Y_ADDR[0])))) # (!Y_ADDR[2] & ((Y_ADDR[3] & (Y_ADDR[1] $ (!Y_ADDR[0]))) # (!Y_ADDR[3] & (Y_ADDR[1] & !Y_ADDR[0]))))

	.dataa(Y_ADDR[2]),
	.datab(Y_ADDR[3]),
	.datac(Y_ADDR[1]),
	.datad(Y_ADDR[0]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[0][8]~7_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[0][8]~7 .lut_mask = 16'h4294;
defparam \Mult0|mult_core|romout[0][8]~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N12
cycloneive_lcell_comb \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 (
// Equation(s):
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout  = (Y_ADDR[4] & (\Mult0|mult_core|romout[0][8]~7_combout  $ (VCC))) # (!Y_ADDR[4] & (\Mult0|mult_core|romout[0][8]~7_combout  & VCC))
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1  = CARRY((Y_ADDR[4] & \Mult0|mult_core|romout[0][8]~7_combout ))

	.dataa(Y_ADDR[4]),
	.datab(\Mult0|mult_core|romout[0][8]~7_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ),
	.cout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ));
// synopsys translate_off
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688;
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N14
cycloneive_lcell_comb \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 (
// Equation(s):
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  = (\Mult0|mult_core|romout[0][9]~6_combout  & ((\Mult0|mult_core|romout[1][5]~5_combout  & (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1  & VCC)) # 
// (!\Mult0|mult_core|romout[1][5]~5_combout  & (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )))) # (!\Mult0|mult_core|romout[0][9]~6_combout  & ((\Mult0|mult_core|romout[1][5]~5_combout  & (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 
// )) # (!\Mult0|mult_core|romout[1][5]~5_combout  & ((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (GND)))))
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3  = CARRY((\Mult0|mult_core|romout[0][9]~6_combout  & (!\Mult0|mult_core|romout[1][5]~5_combout  & !\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )) # (!\Mult0|mult_core|romout[0][9]~6_combout 
//  & ((!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (!\Mult0|mult_core|romout[1][5]~5_combout ))))

	.dataa(\Mult0|mult_core|romout[0][9]~6_combout ),
	.datab(\Mult0|mult_core|romout[1][5]~5_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ),
	.combout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ),
	.cout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ));
// synopsys translate_off
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617;
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N16
cycloneive_lcell_comb \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 (
// Equation(s):
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout  = ((\Mult0|mult_core|romout[1][6]~3_combout  $ (\Mult0|mult_core|romout[0][10]~4_combout  $ (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )))) # (GND)
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5  = CARRY((\Mult0|mult_core|romout[1][6]~3_combout  & ((\Mult0|mult_core|romout[0][10]~4_combout ) # (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ))) # 
// (!\Mult0|mult_core|romout[1][6]~3_combout  & (\Mult0|mult_core|romout[0][10]~4_combout  & !\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )))

	.dataa(\Mult0|mult_core|romout[1][6]~3_combout ),
	.datab(\Mult0|mult_core|romout[0][10]~4_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ),
	.combout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ),
	.cout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ));
// synopsys translate_off
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .lut_mask = 16'h698E;
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N18
cycloneive_lcell_comb \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 (
// Equation(s):
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  = (\Mult0|mult_core|_~0_combout  & ((\Mult0|mult_core|romout[1][7]~2_combout  & (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5  & VCC)) # (!\Mult0|mult_core|romout[1][7]~2_combout  & 
// (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )))) # (!\Mult0|mult_core|_~0_combout  & ((\Mult0|mult_core|romout[1][7]~2_combout  & (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) # (!\Mult0|mult_core|romout[1][7]~2_combout  & 
// ((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (GND)))))
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7  = CARRY((\Mult0|mult_core|_~0_combout  & (!\Mult0|mult_core|romout[1][7]~2_combout  & !\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) # (!\Mult0|mult_core|_~0_combout  & 
// ((!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (!\Mult0|mult_core|romout[1][7]~2_combout ))))

	.dataa(\Mult0|mult_core|_~0_combout ),
	.datab(\Mult0|mult_core|romout[1][7]~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ),
	.combout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ),
	.cout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ));
// synopsys translate_off
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617;
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N20
cycloneive_lcell_comb \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 (
// Equation(s):
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout  = (\Mult0|mult_core|romout[1][8]~1_combout  & (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7  $ (GND))) # (!\Mult0|mult_core|romout[1][8]~1_combout  & 
// (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7  & VCC))
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9  = CARRY((\Mult0|mult_core|romout[1][8]~1_combout  & !\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ))

	.dataa(gnd),
	.datab(\Mult0|mult_core|romout[1][8]~1_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ),
	.combout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ),
	.cout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ));
// synopsys translate_off
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .lut_mask = 16'hC30C;
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N22
cycloneive_lcell_comb \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 (
// Equation(s):
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  = (\Mult0|mult_core|romout[1][9]~0_combout  & (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) # (!\Mult0|mult_core|romout[1][9]~0_combout  & 
// ((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (GND)))
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11  = CARRY((!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (!\Mult0|mult_core|romout[1][9]~0_combout ))

	.dataa(gnd),
	.datab(\Mult0|mult_core|romout[1][9]~0_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ),
	.combout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ),
	.cout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ));
// synopsys translate_off
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h3C3F;
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N18
cycloneive_lcell_comb \Y_ADDR[8]~31 (
// Equation(s):
// \Y_ADDR[8]~31_combout  = (Y_ADDR[8] & (\Y_ADDR[7]~30  $ (GND))) # (!Y_ADDR[8] & (!\Y_ADDR[7]~30  & VCC))
// \Y_ADDR[8]~32  = CARRY((Y_ADDR[8] & !\Y_ADDR[7]~30 ))

	.dataa(gnd),
	.datab(Y_ADDR[8]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[7]~30 ),
	.combout(\Y_ADDR[8]~31_combout ),
	.cout(\Y_ADDR[8]~32 ));
// synopsys translate_off
defparam \Y_ADDR[8]~31 .lut_mask = 16'hC30C;
defparam \Y_ADDR[8]~31 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N19
dffeas \Y_ADDR[8] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[8]~31_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[8]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[8] .is_wysiwyg = "true";
defparam \Y_ADDR[8] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N20
cycloneive_lcell_comb \Y_ADDR[9]~33 (
// Equation(s):
// \Y_ADDR[9]~33_combout  = (Y_ADDR[9] & (!\Y_ADDR[8]~32 )) # (!Y_ADDR[9] & ((\Y_ADDR[8]~32 ) # (GND)))
// \Y_ADDR[9]~34  = CARRY((!\Y_ADDR[8]~32 ) # (!Y_ADDR[9]))

	.dataa(gnd),
	.datab(Y_ADDR[9]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Y_ADDR[8]~32 ),
	.combout(\Y_ADDR[9]~33_combout ),
	.cout(\Y_ADDR[9]~34 ));
// synopsys translate_off
defparam \Y_ADDR[9]~33 .lut_mask = 16'h3C3F;
defparam \Y_ADDR[9]~33 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N21
dffeas \Y_ADDR[9] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[9]~33_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[9]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[9] .is_wysiwyg = "true";
defparam \Y_ADDR[9] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X32_Y17_N0
cycloneive_lcell_comb \Mult0|mult_core|romout[2][5] (
// Equation(s):
// \Mult0|mult_core|romout[2][5]~combout  = Y_ADDR[9] $ (Y_ADDR[8])

	.dataa(gnd),
	.datab(gnd),
	.datac(Y_ADDR[9]),
	.datad(Y_ADDR[8]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[2][5]~combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[2][5] .lut_mask = 16'h0FF0;
defparam \Mult0|mult_core|romout[2][5] .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N26
cycloneive_lcell_comb \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 (
// Equation(s):
// \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout  = (Y_ADDR[8] & (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout  $ (VCC))) # (!Y_ADDR[8] & (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout  & VCC))
// \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1  = CARRY((Y_ADDR[8] & \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ))

	.dataa(Y_ADDR[8]),
	.datab(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ),
	.cout(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ));
// synopsys translate_off
defparam \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688;
defparam \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N28
cycloneive_lcell_comb \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 (
// Equation(s):
// \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  = (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  & ((\Mult0|mult_core|romout[2][5]~combout  & 
// (\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1  & VCC)) # (!\Mult0|mult_core|romout[2][5]~combout  & (!\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )))) # 
// (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  & ((\Mult0|mult_core|romout[2][5]~combout  & (!\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )) # (!\Mult0|mult_core|romout[2][5]~combout  & 
// ((\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (GND)))))
// \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  = CARRY((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  & (!\Mult0|mult_core|romout[2][5]~combout  & !\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 
// )) # (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout  & ((!\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (!\Mult0|mult_core|romout[2][5]~combout ))))

	.dataa(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ),
	.datab(\Mult0|mult_core|romout[2][5]~combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ),
	.combout(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
	.cout(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ));
// synopsys translate_off
defparam \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617;
defparam \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N28
cycloneive_lcell_comb \Mult0|mult_core|romout[0][7]~8 (
// Equation(s):
// \Mult0|mult_core|romout[0][7]~8_combout  = Y_ADDR[3] $ (((Y_ADDR[2] & (Y_ADDR[1] $ (!Y_ADDR[0]))) # (!Y_ADDR[2] & (!Y_ADDR[1] & Y_ADDR[0]))))

	.dataa(Y_ADDR[2]),
	.datab(Y_ADDR[3]),
	.datac(Y_ADDR[1]),
	.datad(Y_ADDR[0]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[0][7]~8_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[0][7]~8 .lut_mask = 16'h69C6;
defparam \Mult0|mult_core|romout[0][7]~8 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N30
cycloneive_lcell_comb \Mult0|mult_core|romout[0][6]~9 (
// Equation(s):
// \Mult0|mult_core|romout[0][6]~9_combout  = Y_ADDR[2] $ (((Y_ADDR[1] & !Y_ADDR[0])))

	.dataa(Y_ADDR[2]),
	.datab(gnd),
	.datac(Y_ADDR[1]),
	.datad(Y_ADDR[0]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[0][6]~9_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[0][6]~9 .lut_mask = 16'hAA5A;
defparam \Mult0|mult_core|romout[0][6]~9 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N0
cycloneive_lcell_comb \Mult0|mult_core|romout[0][5]~10 (
// Equation(s):
// \Mult0|mult_core|romout[0][5]~10_combout  = Y_ADDR[0] $ (Y_ADDR[1])

	.dataa(gnd),
	.datab(gnd),
	.datac(Y_ADDR[0]),
	.datad(Y_ADDR[1]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[0][5]~10_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[0][5]~10 .lut_mask = 16'h0FF0;
defparam \Mult0|mult_core|romout[0][5]~10 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N6
cycloneive_lcell_comb \Add0~0 (
// Equation(s):
// \Add0~0_combout  = (Y_ADDR[0] & (X_ADDR[4] $ (VCC))) # (!Y_ADDR[0] & (X_ADDR[4] & VCC))
// \Add0~1  = CARRY((Y_ADDR[0] & X_ADDR[4]))

	.dataa(Y_ADDR[0]),
	.datab(X_ADDR[4]),
	.datac(gnd),
	.datad(vcc),
	.cin(gnd),
	.combout(\Add0~0_combout ),
	.cout(\Add0~1 ));
// synopsys translate_off
defparam \Add0~0 .lut_mask = 16'h6688;
defparam \Add0~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N8
cycloneive_lcell_comb \Add0~2 (
// Equation(s):
// \Add0~2_combout  = (X_ADDR[5] & ((\Mult0|mult_core|romout[0][5]~10_combout  & (\Add0~1  & VCC)) # (!\Mult0|mult_core|romout[0][5]~10_combout  & (!\Add0~1 )))) # (!X_ADDR[5] & ((\Mult0|mult_core|romout[0][5]~10_combout  & (!\Add0~1 )) # 
// (!\Mult0|mult_core|romout[0][5]~10_combout  & ((\Add0~1 ) # (GND)))))
// \Add0~3  = CARRY((X_ADDR[5] & (!\Mult0|mult_core|romout[0][5]~10_combout  & !\Add0~1 )) # (!X_ADDR[5] & ((!\Add0~1 ) # (!\Mult0|mult_core|romout[0][5]~10_combout ))))

	.dataa(X_ADDR[5]),
	.datab(\Mult0|mult_core|romout[0][5]~10_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~1 ),
	.combout(\Add0~2_combout ),
	.cout(\Add0~3 ));
// synopsys translate_off
defparam \Add0~2 .lut_mask = 16'h9617;
defparam \Add0~2 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N10
cycloneive_lcell_comb \Add0~4 (
// Equation(s):
// \Add0~4_combout  = ((\Mult0|mult_core|romout[0][6]~9_combout  $ (X_ADDR[6] $ (!\Add0~3 )))) # (GND)
// \Add0~5  = CARRY((\Mult0|mult_core|romout[0][6]~9_combout  & ((X_ADDR[6]) # (!\Add0~3 ))) # (!\Mult0|mult_core|romout[0][6]~9_combout  & (X_ADDR[6] & !\Add0~3 )))

	.dataa(\Mult0|mult_core|romout[0][6]~9_combout ),
	.datab(X_ADDR[6]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~3 ),
	.combout(\Add0~4_combout ),
	.cout(\Add0~5 ));
// synopsys translate_off
defparam \Add0~4 .lut_mask = 16'h698E;
defparam \Add0~4 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N12
cycloneive_lcell_comb \Add0~6 (
// Equation(s):
// \Add0~6_combout  = (X_ADDR[7] & ((\Mult0|mult_core|romout[0][7]~8_combout  & (\Add0~5  & VCC)) # (!\Mult0|mult_core|romout[0][7]~8_combout  & (!\Add0~5 )))) # (!X_ADDR[7] & ((\Mult0|mult_core|romout[0][7]~8_combout  & (!\Add0~5 )) # 
// (!\Mult0|mult_core|romout[0][7]~8_combout  & ((\Add0~5 ) # (GND)))))
// \Add0~7  = CARRY((X_ADDR[7] & (!\Mult0|mult_core|romout[0][7]~8_combout  & !\Add0~5 )) # (!X_ADDR[7] & ((!\Add0~5 ) # (!\Mult0|mult_core|romout[0][7]~8_combout ))))

	.dataa(X_ADDR[7]),
	.datab(\Mult0|mult_core|romout[0][7]~8_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~5 ),
	.combout(\Add0~6_combout ),
	.cout(\Add0~7 ));
// synopsys translate_off
defparam \Add0~6 .lut_mask = 16'h9617;
defparam \Add0~6 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N14
cycloneive_lcell_comb \Add0~8 (
// Equation(s):
// \Add0~8_combout  = ((X_ADDR[8] $ (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout  $ (!\Add0~7 )))) # (GND)
// \Add0~9  = CARRY((X_ADDR[8] & ((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ) # (!\Add0~7 ))) # (!X_ADDR[8] & (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout  & !\Add0~7 )))

	.dataa(X_ADDR[8]),
	.datab(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~7 ),
	.combout(\Add0~8_combout ),
	.cout(\Add0~9 ));
// synopsys translate_off
defparam \Add0~8 .lut_mask = 16'h698E;
defparam \Add0~8 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N16
cycloneive_lcell_comb \Add0~10 (
// Equation(s):
// \Add0~10_combout  = (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  & ((X_ADDR[9] & (\Add0~9  & VCC)) # (!X_ADDR[9] & (!\Add0~9 )))) # (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  & ((X_ADDR[9] & (!\Add0~9 )) # 
// (!X_ADDR[9] & ((\Add0~9 ) # (GND)))))
// \Add0~11  = CARRY((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  & (!X_ADDR[9] & !\Add0~9 )) # (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout  & ((!\Add0~9 ) # (!X_ADDR[9]))))

	.dataa(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ),
	.datab(X_ADDR[9]),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~9 ),
	.combout(\Add0~10_combout ),
	.cout(\Add0~11 ));
// synopsys translate_off
defparam \Add0~10 .lut_mask = 16'h9617;
defparam \Add0~10 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N18
cycloneive_lcell_comb \Add0~12 (
// Equation(s):
// \Add0~12_combout  = ((X_ADDR[10] $ (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout  $ (!\Add0~11 )))) # (GND)
// \Add0~13  = CARRY((X_ADDR[10] & ((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ) # (!\Add0~11 ))) # (!X_ADDR[10] & (\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout  & !\Add0~11 )))

	.dataa(X_ADDR[10]),
	.datab(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~11 ),
	.combout(\Add0~12_combout ),
	.cout(\Add0~13 ));
// synopsys translate_off
defparam \Add0~12 .lut_mask = 16'h698E;
defparam \Add0~12 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N20
cycloneive_lcell_comb \Add0~14 (
// Equation(s):
// \Add0~14_combout  = (X_ADDR[11] & ((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  & (\Add0~13  & VCC)) # (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  & (!\Add0~13 )))) # (!X_ADDR[11] & 
// ((\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  & (!\Add0~13 )) # (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  & ((\Add0~13 ) # (GND)))))
// \Add0~15  = CARRY((X_ADDR[11] & (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout  & !\Add0~13 )) # (!X_ADDR[11] & ((!\Add0~13 ) # (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ))))

	.dataa(X_ADDR[11]),
	.datab(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~13 ),
	.combout(\Add0~14_combout ),
	.cout(\Add0~15 ));
// synopsys translate_off
defparam \Add0~14 .lut_mask = 16'h9617;
defparam \Add0~14 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N22
cycloneive_lcell_comb \Add0~16 (
// Equation(s):
// \Add0~16_combout  = ((X_ADDR[12] $ (\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout  $ (!\Add0~15 )))) # (GND)
// \Add0~17  = CARRY((X_ADDR[12] & ((\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ) # (!\Add0~15 ))) # (!X_ADDR[12] & (\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout  & !\Add0~15 )))

	.dataa(X_ADDR[12]),
	.datab(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~15 ),
	.combout(\Add0~16_combout ),
	.cout(\Add0~17 ));
// synopsys translate_off
defparam \Add0~16 .lut_mask = 16'h698E;
defparam \Add0~16 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N24
cycloneive_lcell_comb \Add0~18 (
// Equation(s):
// \Add0~18_combout  = (X_ADDR[13] & ((\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\Add0~17  & VCC)) # (!\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\Add0~17 )))) # (!X_ADDR[13] & 
// ((\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\Add0~17 )) # (!\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\Add0~17 ) # (GND)))))
// \Add0~19  = CARRY((X_ADDR[13] & (!\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & !\Add0~17 )) # (!X_ADDR[13] & ((!\Add0~17 ) # (!\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ))))

	.dataa(X_ADDR[13]),
	.datab(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
	.datac(gnd),
	.datad(vcc),
	.cin(\Add0~17 ),
	.combout(\Add0~18_combout ),
	.cout(\Add0~19 ));
// synopsys translate_off
defparam \Add0~18 .lut_mask = 16'h9617;
defparam \Add0~18 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X30_Y18_N30
cycloneive_lcell_comb \X_ADDR[14]~44 (
// Equation(s):
// \X_ADDR[14]~44_combout  = X_ADDR[14] $ (!\X_ADDR[13]~42 )

	.dataa(X_ADDR[14]),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(\X_ADDR[13]~42 ),
	.combout(\X_ADDR[14]~44_combout ),
	.cout());
// synopsys translate_off
defparam \X_ADDR[14]~44 .lut_mask = 16'hA5A5;
defparam \X_ADDR[14]~44 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X30_Y18_N31
dffeas \X_ADDR[14] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\X_ADDR[14]~44_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(!\GPIO_1_D[33]~input_o ),
	.sload(gnd),
	.ena(\X_ADDR[13]~43_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(X_ADDR[14]),
	.prn(vcc));
// synopsys translate_off
defparam \X_ADDR[14] .is_wysiwyg = "true";
defparam \X_ADDR[14] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X34_Y18_N22
cycloneive_lcell_comb \Y_ADDR[10]~35 (
// Equation(s):
// \Y_ADDR[10]~35_combout  = Y_ADDR[10] $ (!\Y_ADDR[9]~34 )

	.dataa(Y_ADDR[10]),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(\Y_ADDR[9]~34 ),
	.combout(\Y_ADDR[10]~35_combout ),
	.cout());
// synopsys translate_off
defparam \Y_ADDR[10]~35 .lut_mask = 16'hA5A5;
defparam \Y_ADDR[10]~35 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: FF_X34_Y18_N23
dffeas \Y_ADDR[10] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\Y_ADDR[10]~35_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(\always0~0_combout ),
	.sload(gnd),
	.ena(!\GPIO_1_D[33]~input_o ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(Y_ADDR[10]),
	.prn(vcc));
// synopsys translate_off
defparam \Y_ADDR[10] .is_wysiwyg = "true";
defparam \Y_ADDR[10] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X32_Y17_N10
cycloneive_lcell_comb \Mult0|mult_core|romout[2][6]~12 (
// Equation(s):
// \Mult0|mult_core|romout[2][6]~12_combout  = Y_ADDR[10] $ (((!Y_ADDR[8] & Y_ADDR[9])))

	.dataa(gnd),
	.datab(Y_ADDR[8]),
	.datac(Y_ADDR[9]),
	.datad(Y_ADDR[10]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[2][6]~12_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[2][6]~12 .lut_mask = 16'hCF30;
defparam \Mult0|mult_core|romout[2][6]~12 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N10
cycloneive_lcell_comb \Mult0|mult_core|romout[1][10]~11 (
// Equation(s):
// \Mult0|mult_core|romout[1][10]~11_combout  = (Y_ADDR[6] & (!Y_ADDR[7] & Y_ADDR[5])) # (!Y_ADDR[6] & (Y_ADDR[7]))

	.dataa(Y_ADDR[6]),
	.datab(gnd),
	.datac(Y_ADDR[7]),
	.datad(Y_ADDR[5]),
	.cin(gnd),
	.combout(\Mult0|mult_core|romout[1][10]~11_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|romout[1][10]~11 .lut_mask = 16'h5A50;
defparam \Mult0|mult_core|romout[1][10]~11 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N24
cycloneive_lcell_comb \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 (
// Equation(s):
// \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout  = \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11  $ (!\Mult0|mult_core|romout[1][10]~11_combout )

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\Mult0|mult_core|romout[1][10]~11_combout ),
	.cin(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ),
	.combout(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hF00F;
defparam \Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X32_Y18_N30
cycloneive_lcell_comb \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 (
// Equation(s):
// \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  = \Mult0|mult_core|romout[2][6]~12_combout  $ (\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  $ 
// (!\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ))

	.dataa(\Mult0|mult_core|romout[2][6]~12_combout ),
	.datab(gnd),
	.datac(gnd),
	.datad(\Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ),
	.cin(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ),
	.combout(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
	.cout());
// synopsys translate_off
defparam \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'h5AA5;
defparam \Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N26
cycloneive_lcell_comb \Add0~20 (
// Equation(s):
// \Add0~20_combout  = X_ADDR[14] $ (\Add0~19  $ (!\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ))

	.dataa(gnd),
	.datab(X_ADDR[14]),
	.datac(gnd),
	.datad(\Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
	.cin(\Add0~19 ),
	.combout(\Add0~20_combout ),
	.cout());
// synopsys translate_off
defparam \Add0~20 .lut_mask = 16'h3CC3;
defparam \Add0~20 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X34_Y15_N2
cycloneive_lcell_comb \W_EN~0 (
// Equation(s):
// \W_EN~0_combout  = (\is_lsb~q  & \GPIO_1_D[33]~input_o )

	.dataa(gnd),
	.datab(gnd),
	.datac(\is_lsb~q ),
	.datad(\GPIO_1_D[33]~input_o ),
	.cin(gnd),
	.combout(\W_EN~0_combout ),
	.cout());
// synopsys translate_off
defparam \W_EN~0 .lut_mask = 16'hF000;
defparam \W_EN~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X34_Y15_N16
cycloneive_lcell_comb \W_EN~feeder (
// Equation(s):
// \W_EN~feeder_combout  = \W_EN~0_combout 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\W_EN~0_combout ),
	.cin(gnd),
	.combout(\W_EN~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \W_EN~feeder .lut_mask = 16'hFF00;
defparam \W_EN~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X34_Y15_N17
dffeas W_EN(
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\W_EN~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\W_EN~q ),
	.prn(vcc));
// synopsys translate_off
defparam W_EN.is_wysiwyg = "true";
defparam W_EN.power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N4
cycloneive_lcell_comb \mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0 (
// Equation(s):
// \mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout  = (!\Add0~18_combout  & (!\Add0~20_combout  & \W_EN~q ))

	.dataa(gnd),
	.datab(\Add0~18_combout ),
	.datac(\Add0~20_combout ),
	.datad(\W_EN~q ),
	.cin(gnd),
	.combout(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.cout());
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0 .lut_mask = 16'h0300;
defparam \mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: CLKCTRL_G17
cycloneive_clkctrl \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl (
	.ena(vcc),
	.inclk({vcc,vcc,vcc,\PLL_inst|altpll_component|auto_generated|wire_pll1_clk [2]}),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ));
// synopsys translate_off
defparam \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock";
defparam \PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N24
cycloneive_lcell_comb \Mult1|mult_core|romout[1][10]~12 (
// Equation(s):
// \Mult1|mult_core|romout[1][10]~12_combout  = (\driver|line_count [7] & (!\driver|line_count [6])) # (!\driver|line_count [7] & (\driver|line_count [6] & \driver|line_count [5]))

	.dataa(gnd),
	.datab(\driver|line_count [7]),
	.datac(\driver|line_count [6]),
	.datad(\driver|line_count [5]),
	.cin(gnd),
	.combout(\Mult1|mult_core|romout[1][10]~12_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|romout[1][10]~12 .lut_mask = 16'h3C0C;
defparam \Mult1|mult_core|romout[1][10]~12 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N14
cycloneive_lcell_comb \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~12 (
// Equation(s):
// \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~12_combout  = \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~11  $ (!\Mult1|mult_core|romout[1][10]~12_combout )

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\Mult1|mult_core|romout[1][10]~12_combout ),
	.cin(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~11 ),
	.combout(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hF00F;
defparam \Mult1|mult_core|padder|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N4
cycloneive_lcell_comb \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 (
// Equation(s):
// \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  = \Mult1|mult_core|_~1_combout  $ (\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~12_combout  $ (!\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ))

	.dataa(\Mult1|mult_core|_~1_combout ),
	.datab(\Mult1|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ),
	.datac(gnd),
	.datad(gnd),
	.cin(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ),
	.combout(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
	.cout());
// synopsys translate_off
defparam \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'h6969;
defparam \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N26
cycloneive_lcell_comb \Add3~20 (
// Equation(s):
// \Add3~20_combout  = \Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  $ (!\Add3~19 )

	.dataa(gnd),
	.datab(\Mult1|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
	.datac(gnd),
	.datad(gnd),
	.cin(\Add3~19 ),
	.combout(\Add3~20_combout ),
	.cout());
// synopsys translate_off
defparam \Add3~20 .lut_mask = 16'hC3C3;
defparam \Add3~20 .sum_lutc_input = "cin";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N20
cycloneive_lcell_comb \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w[2] (
// Equation(s):
// \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2] = (!\Add3~20_combout  & !\Add3~18_combout )

	.dataa(gnd),
	.datab(gnd),
	.datac(\Add3~20_combout ),
	.datad(\Add3~18_combout ),
	.cin(gnd),
	.combout(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.cout());
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w[2] .lut_mask = 16'h000F;
defparam \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w[2] .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X53_Y6_N22
cycloneive_io_ibuf \GPIO_1_D[27]~input (
	.i(GPIO_1_D[27]),
	.ibar(gnd),
	.o(\GPIO_1_D[27]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[27]~input .bus_hold = "false";
defparam \GPIO_1_D[27]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X34_Y11_N0
cycloneive_lcell_comb \pixel_data_RGB332[7]~feeder (
// Equation(s):
// \pixel_data_RGB332[7]~feeder_combout  = \GPIO_1_D[27]~input_o 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\GPIO_1_D[27]~input_o ),
	.cin(gnd),
	.combout(\pixel_data_RGB332[7]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \pixel_data_RGB332[7]~feeder .lut_mask = 16'hFF00;
defparam \pixel_data_RGB332[7]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X34_Y11_N1
dffeas \pixel_data_RGB332[7] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\pixel_data_RGB332[7]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\W_EN~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(pixel_data_RGB332[7]),
	.prn(vcc));
// synopsys translate_off
defparam \pixel_data_RGB332[7] .is_wysiwyg = "true";
defparam \pixel_data_RGB332[7] .power_up = "low";
// synopsys translate_on

// Location: M9K_X22_Y19_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a7 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[7]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a7 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N2
cycloneive_lcell_comb \mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0 (
// Equation(s):
// \mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout  = (\Add0~18_combout  & (!\Add0~20_combout  & \W_EN~q ))

	.dataa(gnd),
	.datab(\Add0~18_combout ),
	.datac(\Add0~20_combout ),
	.datad(\W_EN~q ),
	.cin(gnd),
	.combout(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.cout());
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0 .lut_mask = 16'h0C00;
defparam \mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N18
cycloneive_lcell_comb \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w[2] (
// Equation(s):
// \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2] = (!\Add3~20_combout  & \Add3~18_combout )

	.dataa(gnd),
	.datab(gnd),
	.datac(\Add3~20_combout ),
	.datad(\Add3~18_combout ),
	.cin(gnd),
	.combout(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.cout());
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w[2] .lut_mask = 16'h0F00;
defparam \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w[2] .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y17_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a15 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[7]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_first_bit_number = 7;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_first_bit_number = 7;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a15 .ram_block_type = "M9K";
// synopsys translate_on

// Location: FF_X28_Y10_N27
dffeas \mem|mem_rtl_0|auto_generated|address_reg_b[1] (
	.clk(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.d(\Add3~20_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.prn(vcc));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|address_reg_b[1] .is_wysiwyg = "true";
defparam \mem|mem_rtl_0|auto_generated|address_reg_b[1] .power_up = "low";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N16
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[7]~2 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[7]~2_combout  = (!\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a15~portbdataout ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a7~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|ram_block1a7~portbdataout ),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a15~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[7]~2_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[7]~2 .lut_mask = 16'h00E4;
defparam \driver|PIXEL_COLOR_OUT[7]~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N30
cycloneive_lcell_comb \mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0 (
// Equation(s):
// \mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout  = (!\Add0~18_combout  & (\Add0~20_combout  & \W_EN~q ))

	.dataa(gnd),
	.datab(\Add0~18_combout ),
	.datac(\Add0~20_combout ),
	.datad(\W_EN~q ),
	.cin(gnd),
	.combout(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.cout());
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0 .lut_mask = 16'h3000;
defparam \mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N30
cycloneive_lcell_comb \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w[2] (
// Equation(s):
// \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2] = (\Add3~20_combout  & !\Add3~18_combout )

	.dataa(gnd),
	.datab(gnd),
	.datac(\Add3~20_combout ),
	.datad(\Add3~18_combout ),
	.cin(gnd),
	.combout(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.cout());
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w[2] .lut_mask = 16'h00F0;
defparam \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w[2] .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y16_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a23 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[7]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a23_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_first_bit_number = 7;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_first_bit_number = 7;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a23 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X31_Y18_N28
cycloneive_lcell_comb \mem|mem_rtl_0|auto_generated|decode2|w_anode329w[2]~0 (
// Equation(s):
// \mem|mem_rtl_0|auto_generated|decode2|w_anode329w[2]~0_combout  = (\Add0~18_combout  & (\Add0~20_combout  & \W_EN~q ))

	.dataa(gnd),
	.datab(\Add0~18_combout ),
	.datac(\Add0~20_combout ),
	.datad(\W_EN~q ),
	.cin(gnd),
	.combout(\mem|mem_rtl_0|auto_generated|decode2|w_anode329w[2]~0_combout ),
	.cout());
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|decode2|w_anode329w[2]~0 .lut_mask = 16'hC000;
defparam \mem|mem_rtl_0|auto_generated|decode2|w_anode329w[2]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X29_Y10_N30
cycloneive_lcell_comb \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode370w[2] (
// Equation(s):
// \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode370w [2] = (\Add3~20_combout  & \Add3~18_combout )

	.dataa(gnd),
	.datab(gnd),
	.datac(\Add3~20_combout ),
	.datad(\Add3~18_combout ),
	.cin(gnd),
	.combout(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode370w [2]),
	.cout());
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode370w[2] .lut_mask = 16'hF000;
defparam \mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode370w[2] .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X53_Y9_N22
cycloneive_io_ibuf \GPIO_1_D[23]~input (
	.i(GPIO_1_D[23]),
	.ibar(gnd),
	.o(\GPIO_1_D[23]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[23]~input .bus_hold = "false";
defparam \GPIO_1_D[23]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X34_Y11_N30
cycloneive_lcell_comb \pixel_data_RGB332[0]~feeder (
// Equation(s):
// \pixel_data_RGB332[0]~feeder_combout  = \GPIO_1_D[23]~input_o 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\GPIO_1_D[23]~input_o ),
	.cin(gnd),
	.combout(\pixel_data_RGB332[0]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \pixel_data_RGB332[0]~feeder .lut_mask = 16'hFF00;
defparam \pixel_data_RGB332[0]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X34_Y11_N31
dffeas \pixel_data_RGB332[0] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\pixel_data_RGB332[0]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\pixel_data_RGB332[0]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(pixel_data_RGB332[0]),
	.prn(vcc));
// synopsys translate_off
defparam \pixel_data_RGB332[0] .is_wysiwyg = "true";
defparam \pixel_data_RGB332[0] .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X53_Y9_N15
cycloneive_io_ibuf \GPIO_1_D[24]~input (
	.i(GPIO_1_D[24]),
	.ibar(gnd),
	.o(\GPIO_1_D[24]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[24]~input .bus_hold = "false";
defparam \GPIO_1_D[24]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X34_Y11_N20
cycloneive_lcell_comb \pixel_data_RGB332[1]~feeder (
// Equation(s):
// \pixel_data_RGB332[1]~feeder_combout  = \GPIO_1_D[24]~input_o 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\GPIO_1_D[24]~input_o ),
	.cin(gnd),
	.combout(\pixel_data_RGB332[1]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \pixel_data_RGB332[1]~feeder .lut_mask = 16'hFF00;
defparam \pixel_data_RGB332[1]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X34_Y11_N21
dffeas \pixel_data_RGB332[1] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\pixel_data_RGB332[1]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\pixel_data_RGB332[0]~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(pixel_data_RGB332[1]),
	.prn(vcc));
// synopsys translate_off
defparam \pixel_data_RGB332[1] .is_wysiwyg = "true";
defparam \pixel_data_RGB332[1] .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X53_Y6_N15
cycloneive_io_ibuf \GPIO_1_D[20]~input (
	.i(GPIO_1_D[20]),
	.ibar(gnd),
	.o(\GPIO_1_D[20]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[20]~input .bus_hold = "false";
defparam \GPIO_1_D[20]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X34_Y11_N11
dffeas \pixel_data_RGB332[2] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(gnd),
	.asdata(\GPIO_1_D[20]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\W_EN~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(pixel_data_RGB332[2]),
	.prn(vcc));
// synopsys translate_off
defparam \pixel_data_RGB332[2] .is_wysiwyg = "true";
defparam \pixel_data_RGB332[2] .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X53_Y7_N8
cycloneive_io_ibuf \GPIO_1_D[21]~input (
	.i(GPIO_1_D[21]),
	.ibar(gnd),
	.o(\GPIO_1_D[21]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[21]~input .bus_hold = "false";
defparam \GPIO_1_D[21]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X34_Y11_N9
dffeas \pixel_data_RGB332[3] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(gnd),
	.asdata(\GPIO_1_D[21]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\W_EN~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(pixel_data_RGB332[3]),
	.prn(vcc));
// synopsys translate_off
defparam \pixel_data_RGB332[3] .is_wysiwyg = "true";
defparam \pixel_data_RGB332[3] .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X49_Y0_N1
cycloneive_io_ibuf \GPIO_1_D[22]~input (
	.i(GPIO_1_D[22]),
	.ibar(gnd),
	.o(\GPIO_1_D[22]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[22]~input .bus_hold = "false";
defparam \GPIO_1_D[22]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X34_Y11_N22
cycloneive_lcell_comb \pixel_data_RGB332[4]~feeder (
// Equation(s):
// \pixel_data_RGB332[4]~feeder_combout  = \GPIO_1_D[22]~input_o 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\GPIO_1_D[22]~input_o ),
	.cin(gnd),
	.combout(\pixel_data_RGB332[4]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \pixel_data_RGB332[4]~feeder .lut_mask = 16'hFF00;
defparam \pixel_data_RGB332[4]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// Location: FF_X34_Y11_N23
dffeas \pixel_data_RGB332[4] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(\pixel_data_RGB332[4]~feeder_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\W_EN~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(pixel_data_RGB332[4]),
	.prn(vcc));
// synopsys translate_off
defparam \pixel_data_RGB332[4] .is_wysiwyg = "true";
defparam \pixel_data_RGB332[4] .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X49_Y0_N8
cycloneive_io_ibuf \GPIO_1_D[25]~input (
	.i(GPIO_1_D[25]),
	.ibar(gnd),
	.o(\GPIO_1_D[25]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[25]~input .bus_hold = "false";
defparam \GPIO_1_D[25]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X34_Y11_N13
dffeas \pixel_data_RGB332[5] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(gnd),
	.asdata(\GPIO_1_D[25]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\W_EN~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(pixel_data_RGB332[5]),
	.prn(vcc));
// synopsys translate_off
defparam \pixel_data_RGB332[5] .is_wysiwyg = "true";
defparam \pixel_data_RGB332[5] .power_up = "low";
// synopsys translate_on

// Location: IOIBUF_X53_Y9_N8
cycloneive_io_ibuf \GPIO_1_D[26]~input (
	.i(GPIO_1_D[26]),
	.ibar(gnd),
	.o(\GPIO_1_D[26]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[26]~input .bus_hold = "false";
defparam \GPIO_1_D[26]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: FF_X34_Y11_N27
dffeas \pixel_data_RGB332[6] (
	.clk(\GPIO_1_D[32]~input_o ),
	.d(gnd),
	.asdata(\GPIO_1_D[26]~input_o ),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\W_EN~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(pixel_data_RGB332[6]),
	.prn(vcc));
// synopsys translate_off
defparam \pixel_data_RGB332[6] .is_wysiwyg = "true";
defparam \pixel_data_RGB332[6] .power_up = "low";
// synopsys translate_on

// Location: M9K_X33_Y12_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a24 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode329w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode329w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode370w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({gnd,pixel_data_RGB332[7],pixel_data_RGB332[6],pixel_data_RGB332[5],pixel_data_RGB332[4],pixel_data_RGB332[3],pixel_data_RGB332[2],pixel_data_RGB332[1],pixel_data_RGB332[0]}),
	.portaaddr({\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(9'b000000000),
	.portbaddr({\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a24_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_address_width = 10;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_data_width = 9;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_first_bit_number = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_last_address = 1023;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_address_width = 10;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_data_width = 9;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_first_bit_number = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_last_address = 1023;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a24 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N26
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[7]~3 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[7]~3_combout  = (\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a31 ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b [0] & 
// (\mem|mem_rtl_0|auto_generated|ram_block1a23~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a23~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a31 ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[7]~3_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[7]~3 .lut_mask = 16'hC840;
defparam \driver|PIXEL_COLOR_OUT[7]~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N22
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[7]~0 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[7]~0_combout  = (!\driver|pixel_count [8] & (!\driver|line_count [9] & !\driver|line_count [8]))

	.dataa(gnd),
	.datab(\driver|pixel_count [8]),
	.datac(\driver|line_count [9]),
	.datad(\driver|line_count [8]),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[7]~0_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[7]~0 .lut_mask = 16'h0003;
defparam \driver|PIXEL_COLOR_OUT[7]~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y10_N28
cycloneive_lcell_comb \LessThan0~0 (
// Equation(s):
// \LessThan0~0_combout  = (\driver|pixel_count [7] & ((\driver|pixel_count [6]) # ((\driver|pixel_count [5] & \driver|pixel_count [4]))))

	.dataa(\driver|pixel_count [6]),
	.datab(\driver|pixel_count [5]),
	.datac(\driver|pixel_count [4]),
	.datad(\driver|pixel_count [7]),
	.cin(gnd),
	.combout(\LessThan0~0_combout ),
	.cout());
// synopsys translate_off
defparam \LessThan0~0 .lut_mask = 16'hEA00;
defparam \LessThan0~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X27_Y10_N2
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[7]~1 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[7]~1_combout  = (\driver|PIXEL_COLOR_OUT[7]~0_combout  & (!\LessThan0~0_combout  & ((\driver|Equal1~0_combout ) # (!\driver|line_count [7]))))

	.dataa(\driver|PIXEL_COLOR_OUT[7]~0_combout ),
	.datab(\driver|Equal1~0_combout ),
	.datac(\driver|line_count [7]),
	.datad(\LessThan0~0_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[7]~1 .lut_mask = 16'h008A;
defparam \driver|PIXEL_COLOR_OUT[7]~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N28
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[7]~4 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[7]~4_combout  = (!\driver|pixel_count [9] & (\driver|PIXEL_COLOR_OUT[7]~1_combout  & ((\driver|PIXEL_COLOR_OUT[7]~2_combout ) # (\driver|PIXEL_COLOR_OUT[7]~3_combout ))))

	.dataa(\driver|pixel_count [9]),
	.datab(\driver|PIXEL_COLOR_OUT[7]~2_combout ),
	.datac(\driver|PIXEL_COLOR_OUT[7]~3_combout ),
	.datad(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[7]~4_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[7]~4 .lut_mask = 16'h5400;
defparam \driver|PIXEL_COLOR_OUT[7]~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y13_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a14 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[6]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_first_bit_number = 6;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_first_bit_number = 6;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a14 .ram_block_type = "M9K";
// synopsys translate_on

// Location: M9K_X22_Y12_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a6 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[6]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a6 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N6
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[6]~5 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[6]~5_combout  = (!\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a14~portbdataout )) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a6~portbdataout )))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|ram_block1a14~portbdataout ),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a6~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[6]~5_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[6]~5 .lut_mask = 16'h00D8;
defparam \driver|PIXEL_COLOR_OUT[6]~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y9_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a22 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[6]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a22_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_first_bit_number = 6;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_first_bit_number = 6;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a22 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N24
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[6]~6 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[6]~6_combout  = (\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a30 ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b [0] & 
// (\mem|mem_rtl_0|auto_generated|ram_block1a22~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a22~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a30 ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[6]~6_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[6]~6 .lut_mask = 16'hC840;
defparam \driver|PIXEL_COLOR_OUT[6]~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N10
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[6]~7 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[6]~7_combout  = (!\driver|pixel_count [9] & (\driver|PIXEL_COLOR_OUT[7]~1_combout  & ((\driver|PIXEL_COLOR_OUT[6]~5_combout ) # (\driver|PIXEL_COLOR_OUT[6]~6_combout ))))

	.dataa(\driver|PIXEL_COLOR_OUT[6]~5_combout ),
	.datab(\driver|PIXEL_COLOR_OUT[6]~6_combout ),
	.datac(\driver|pixel_count [9]),
	.datad(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[6]~7_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[6]~7 .lut_mask = 16'h0E00;
defparam \driver|PIXEL_COLOR_OUT[6]~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y15_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a5 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[5]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a5 .ram_block_type = "M9K";
// synopsys translate_on

// Location: M9K_X22_Y14_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a13 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[5]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_first_bit_number = 5;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_first_bit_number = 5;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a13 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N20
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[5]~8 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[5]~8_combout  = (!\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a13~portbdataout ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a5~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|ram_block1a5~portbdataout ),
	.datab(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a13~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[5]~8_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[5]~8 .lut_mask = 16'h3022;
defparam \driver|PIXEL_COLOR_OUT[5]~8 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y8_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a21 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[5]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a21_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_first_bit_number = 5;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_first_bit_number = 5;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a21 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N22
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[5]~9 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[5]~9_combout  = (\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a29 ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b [0] & 
// (\mem|mem_rtl_0|auto_generated|ram_block1a21~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a21~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a29 ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[5]~9_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[5]~9 .lut_mask = 16'hC840;
defparam \driver|PIXEL_COLOR_OUT[5]~9 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N8
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[5]~10 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[5]~10_combout  = (!\driver|pixel_count [9] & (\driver|PIXEL_COLOR_OUT[7]~1_combout  & ((\driver|PIXEL_COLOR_OUT[5]~8_combout ) # (\driver|PIXEL_COLOR_OUT[5]~9_combout ))))

	.dataa(\driver|pixel_count [9]),
	.datab(\driver|PIXEL_COLOR_OUT[5]~8_combout ),
	.datac(\driver|PIXEL_COLOR_OUT[5]~9_combout ),
	.datad(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[5]~10_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[5]~10 .lut_mask = 16'h5400;
defparam \driver|PIXEL_COLOR_OUT[5]~10 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y9_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a20 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[4]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a20_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_first_bit_number = 4;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_first_bit_number = 4;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a20 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N12
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[4]~12 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[4]~12_combout  = (\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a28 ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b [0] & 
// (\mem|mem_rtl_0|auto_generated|ram_block1a20~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a20~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a28 ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[4]~12_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[4]~12 .lut_mask = 16'hC840;
defparam \driver|PIXEL_COLOR_OUT[4]~12 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y10_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a4 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[4]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a4 .ram_block_type = "M9K";
// synopsys translate_on

// Location: M9K_X33_Y11_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a12 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[4]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_first_bit_number = 4;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_first_bit_number = 4;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a12 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N2
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[4]~11 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[4]~11_combout  = (!\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a12~portbdataout ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a4~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a4~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a12~portbdataout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[4]~11_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[4]~11 .lut_mask = 16'h3210;
defparam \driver|PIXEL_COLOR_OUT[4]~11 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N30
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[4]~13 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[4]~13_combout  = (!\driver|pixel_count [9] & (\driver|PIXEL_COLOR_OUT[7]~1_combout  & ((\driver|PIXEL_COLOR_OUT[4]~12_combout ) # (\driver|PIXEL_COLOR_OUT[4]~11_combout ))))

	.dataa(\driver|PIXEL_COLOR_OUT[4]~12_combout ),
	.datab(\driver|PIXEL_COLOR_OUT[4]~11_combout ),
	.datac(\driver|pixel_count [9]),
	.datad(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[4]~13_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[4]~13 .lut_mask = 16'h0E00;
defparam \driver|PIXEL_COLOR_OUT[4]~13 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y11_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a11 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[3]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_first_bit_number = 3;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_first_bit_number = 3;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a11 .ram_block_type = "M9K";
// synopsys translate_on

// Location: M9K_X22_Y10_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a3 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[3]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a3 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N0
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[3]~14 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[3]~14_combout  = (!\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a11~portbdataout )) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a3~portbdataout )))))

	.dataa(\mem|mem_rtl_0|auto_generated|ram_block1a11~portbdataout ),
	.datab(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a3~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[3]~14_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[3]~14 .lut_mask = 16'h2230;
defparam \driver|PIXEL_COLOR_OUT[3]~14 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y8_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a19 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[3]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a19_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_first_bit_number = 3;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_first_bit_number = 3;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a19 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N18
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[3]~15 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[3]~15_combout  = (\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a27 ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b [0] & 
// (\mem|mem_rtl_0|auto_generated|ram_block1a19~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datac(\mem|mem_rtl_0|auto_generated|ram_block1a19~portbdataout ),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a27 ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[3]~15_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[3]~15 .lut_mask = 16'hC840;
defparam \driver|PIXEL_COLOR_OUT[3]~15 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X23_Y12_N4
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[3]~16 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[3]~16_combout  = (!\driver|pixel_count [9] & (\driver|PIXEL_COLOR_OUT[7]~1_combout  & ((\driver|PIXEL_COLOR_OUT[3]~14_combout ) # (\driver|PIXEL_COLOR_OUT[3]~15_combout ))))

	.dataa(\driver|PIXEL_COLOR_OUT[3]~14_combout ),
	.datab(\driver|PIXEL_COLOR_OUT[3]~15_combout ),
	.datac(\driver|pixel_count [9]),
	.datad(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[3]~16_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[3]~16 .lut_mask = 16'h0E00;
defparam \driver|PIXEL_COLOR_OUT[3]~16 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y16_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a18 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[2]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a18_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_first_bit_number = 2;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_first_bit_number = 2;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a18 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N26
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[2]~18 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[2]~18_combout  = (\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a26 )) # (!\mem|mem_rtl_0|auto_generated|address_reg_b [0] & 
// ((\mem|mem_rtl_0|auto_generated|ram_block1a18~portbdataout )))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|ram_block1a26 ),
	.datac(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a18~portbdataout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[2]~18_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[2]~18 .lut_mask = 16'hD080;
defparam \driver|PIXEL_COLOR_OUT[2]~18 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y18_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a10 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[2]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_first_bit_number = 2;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_first_bit_number = 2;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a10 .ram_block_type = "M9K";
// synopsys translate_on

// Location: M9K_X33_Y21_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a2 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[2]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a2 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N0
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[2]~17 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[2]~17_combout  = (!\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a10~portbdataout )) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a2~portbdataout )))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|ram_block1a10~portbdataout ),
	.datac(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a2~portbdataout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[2]~17_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[2]~17 .lut_mask = 16'h0D08;
defparam \driver|PIXEL_COLOR_OUT[2]~17 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N12
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[2]~19 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[2]~19_combout  = (\driver|PIXEL_COLOR_OUT[7]~1_combout  & (!\driver|pixel_count [9] & ((\driver|PIXEL_COLOR_OUT[2]~18_combout ) # (\driver|PIXEL_COLOR_OUT[2]~17_combout ))))

	.dataa(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.datab(\driver|pixel_count [9]),
	.datac(\driver|PIXEL_COLOR_OUT[2]~18_combout ),
	.datad(\driver|PIXEL_COLOR_OUT[2]~17_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[2]~19_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[2]~19 .lut_mask = 16'h2220;
defparam \driver|PIXEL_COLOR_OUT[2]~19 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y14_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a1 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[1]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a1 .ram_block_type = "M9K";
// synopsys translate_on

// Location: M9K_X33_Y13_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a9 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[1]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_first_bit_number = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_first_bit_number = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a9 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N8
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[1]~21 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[1]~21_combout  = (!\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a9~portbdataout ))) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a1~portbdataout ))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datab(\mem|mem_rtl_0|auto_generated|ram_block1a1~portbdataout ),
	.datac(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a9~portbdataout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[1]~21_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[1]~21 .lut_mask = 16'h5404;
defparam \driver|PIXEL_COLOR_OUT[1]~21 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y15_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a17 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[1]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a17_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_first_bit_number = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_first_bit_number = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a17 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N6
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[1]~20 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[1]~20_combout  = (\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a25 )) # (!\mem|mem_rtl_0|auto_generated|address_reg_b [0] & 
// ((\mem|mem_rtl_0|auto_generated|ram_block1a17~portbdataout )))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datab(\mem|mem_rtl_0|auto_generated|ram_block1a25 ),
	.datac(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a17~portbdataout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[1]~20_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[1]~20 .lut_mask = 16'hD080;
defparam \driver|PIXEL_COLOR_OUT[1]~20 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N10
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[1]~22 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[1]~22_combout  = (!\driver|pixel_count [9] & (((\driver|PIXEL_COLOR_OUT[1]~21_combout ) # (\driver|PIXEL_COLOR_OUT[1]~20_combout )) # (!\driver|PIXEL_COLOR_OUT[7]~1_combout )))

	.dataa(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.datab(\driver|pixel_count [9]),
	.datac(\driver|PIXEL_COLOR_OUT[1]~21_combout ),
	.datad(\driver|PIXEL_COLOR_OUT[1]~20_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[1]~22_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[1]~22 .lut_mask = 16'h3331;
defparam \driver|PIXEL_COLOR_OUT[1]~22 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N20
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[1]~23 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[1]~23_combout  = (\driver|PIXEL_COLOR_OUT[1]~22_combout ) # ((\driver|pixel_count [9] & (!\driver|pixel_count [8] & !\driver|pixel_count [7])))

	.dataa(\driver|PIXEL_COLOR_OUT[1]~22_combout ),
	.datab(\driver|pixel_count [9]),
	.datac(\driver|pixel_count [8]),
	.datad(\driver|pixel_count [7]),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[1]~23_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[1]~23 .lut_mask = 16'hAAAE;
defparam \driver|PIXEL_COLOR_OUT[1]~23 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X33_Y17_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a16 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode321w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode361w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[0]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a16_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_first_bit_number = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_first_bit_number = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a16 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N22
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[0]~24 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[0]~24_combout  = (\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a24~portbdataout )) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a16~portbdataout )))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datab(\mem|mem_rtl_0|auto_generated|ram_block1a24~portbdataout ),
	.datac(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a16~portbdataout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[0]~24_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[0]~24 .lut_mask = 16'h8A80;
defparam \driver|PIXEL_COLOR_OUT[0]~24 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: M9K_X22_Y18_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a8 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode313w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode352w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[0]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_first_bit_number = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_first_bit_number = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a8 .ram_block_type = "M9K";
// synopsys translate_on

// Location: M9K_X33_Y19_N0
cycloneive_ram_block \mem|mem_rtl_0|auto_generated|ram_block1a0 (
	.portawe(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
	.clk1(\PLL_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
	.ena0(\mem|mem_rtl_0|auto_generated|decode2|w_anode300w[2]~0_combout ),
	.ena1(\mem|mem_rtl_0|auto_generated|rden_decode_b|w_anode338w [2]),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({pixel_data_RGB332[0]}),
	.portaaddr({\Add0~16_combout ,\Add0~14_combout ,\Add0~12_combout ,\Add0~10_combout ,\Add0~8_combout ,\Add0~6_combout ,\Add0~4_combout ,\Add0~2_combout ,\Add0~0_combout ,X_ADDR[3],X_ADDR[2],X_ADDR[1],X_ADDR[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({\Add3~16_combout ,\Add3~14_combout ,\Add3~12_combout ,\Add3~10_combout ,\Add3~8_combout ,\Add3~6_combout ,\Add3~4_combout ,\Add3~2_combout ,\Add3~0_combout ,\driver|pixel_count [3],\driver|pixel_count [2],\driver|pixel_count [1],\driver|pixel_count [0]}),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\mem|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .logical_ram_name = "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .operation_mode = "dual_port";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_width = 13;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_width = 1;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_first_address = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_last_address = 8191;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 25344;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \mem|mem_rtl_0|auto_generated|ram_block1a0 .ram_block_type = "M9K";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N24
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[0]~25 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[0]~25_combout  = (!\mem|mem_rtl_0|auto_generated|address_reg_b [1] & ((\mem|mem_rtl_0|auto_generated|address_reg_b [0] & (\mem|mem_rtl_0|auto_generated|ram_block1a8~portbdataout )) # (!\mem|mem_rtl_0|auto_generated|address_reg_b 
// [0] & ((\mem|mem_rtl_0|auto_generated|ram_block1a0~portbdataout )))))

	.dataa(\mem|mem_rtl_0|auto_generated|address_reg_b [1]),
	.datab(\mem|mem_rtl_0|auto_generated|ram_block1a8~portbdataout ),
	.datac(\mem|mem_rtl_0|auto_generated|address_reg_b [0]),
	.datad(\mem|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[0]~25_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[0]~25 .lut_mask = 16'h4540;
defparam \driver|PIXEL_COLOR_OUT[0]~25 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N18
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[0]~26 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[0]~26_combout  = (!\driver|pixel_count [9] & (((\driver|PIXEL_COLOR_OUT[0]~24_combout ) # (\driver|PIXEL_COLOR_OUT[0]~25_combout )) # (!\driver|PIXEL_COLOR_OUT[7]~1_combout )))

	.dataa(\driver|PIXEL_COLOR_OUT[7]~1_combout ),
	.datab(\driver|pixel_count [9]),
	.datac(\driver|PIXEL_COLOR_OUT[0]~24_combout ),
	.datad(\driver|PIXEL_COLOR_OUT[0]~25_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[0]~26_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[0]~26 .lut_mask = 16'h3331;
defparam \driver|PIXEL_COLOR_OUT[0]~26 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y16_N4
cycloneive_lcell_comb \driver|PIXEL_COLOR_OUT[0]~27 (
// Equation(s):
// \driver|PIXEL_COLOR_OUT[0]~27_combout  = (\driver|PIXEL_COLOR_OUT[0]~26_combout ) # ((\driver|pixel_count [9] & (!\driver|pixel_count [7] & !\driver|pixel_count [8])))

	.dataa(\driver|pixel_count [9]),
	.datab(\driver|pixel_count [7]),
	.datac(\driver|pixel_count [8]),
	.datad(\driver|PIXEL_COLOR_OUT[0]~26_combout ),
	.cin(gnd),
	.combout(\driver|PIXEL_COLOR_OUT[0]~27_combout ),
	.cout());
// synopsys translate_off
defparam \driver|PIXEL_COLOR_OUT[0]~27 .lut_mask = 16'hFF02;
defparam \driver|PIXEL_COLOR_OUT[0]~27 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X43_Y0_N22
cycloneive_io_ibuf \GPIO_1_D[28]~input (
	.i(GPIO_1_D[28]),
	.ibar(gnd),
	.o(\GPIO_1_D[28]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[28]~input .bus_hold = "false";
defparam \GPIO_1_D[28]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X53_Y10_N15
cycloneive_io_ibuf \GPIO_1_D[29]~input (
	.i(GPIO_1_D[29]),
	.ibar(gnd),
	.o(\GPIO_1_D[29]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[29]~input .bus_hold = "false";
defparam \GPIO_1_D[29]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X53_Y13_N8
cycloneive_io_ibuf \GPIO_1_D[31]~input (
	.i(GPIO_1_D[31]),
	.ibar(gnd),
	.o(\GPIO_1_D[31]~input_o ));
// synopsys translate_off
defparam \GPIO_1_D[31]~input .bus_hold = "false";
defparam \GPIO_1_D[31]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y16_N8
cycloneive_io_ibuf \KEY[1]~input (
	.i(KEY[1]),
	.ibar(gnd),
	.o(\KEY[1]~input_o ));
// synopsys translate_off
defparam \KEY[1]~input .bus_hold = "false";
defparam \KEY[1]~input .simulate_z_as = "z";
// synopsys translate_on

endmodule
